Patent US4988633A successfully refreshed from Google Patents.
US4988633A
Expired / Lapsed
US
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Method of manufacturing a semiconductor Bi-CMOS device
Assignee: US Philips Corp
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Filing: 1990-06-06
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Granted: 1991-01-29
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Expires: 2010-06-06
Abstract
Abstract The collector region (20) of a bipolar transistor (T) and a first well region (3) for an insulated gate field effect transistor (IGFET) (P) are formed of one conductivity type at respective first and second device areas (10 and 12) of a semiconductor body (1a). After definition of an insulated gate (9), opposite conductivity type impurities are introduced to form source and drain regions (90 and 91) of the IGFET (P) and at the same time to dope a dopable layer (30) on the first device area (10) to form an opposite conductivity type doped layer (30) for forming an extrinsic base region (40). An insulating layer (50, 51) is then provided to cover the first and second device areas (10 and 12). Impurities for forming an intrinsic base region (41) and emitter region (80) of the bipolar transistor (T) are introduced through an opening (60, 61) in the insulating layer (50, 51) which also serves to mask the IGFET (P) from these impurities.
Inventors
- 👤 Wilhelmus J. M. J. Josquin
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 11:44
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/01; H10D84/0107; H10D84/0109; H10D10/00; H10D10/01; H10D10/051; H10D84/02; H10D84/03; H10D84/038
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
247 words
A method of manufacturing a semiconductor device comprising a bipolar transistor and an insulated gate field effect transistor, which method comprises providing a semiconductor body having, adjacent to one major surface, a collector region of one conductivity type at a first device area and a first well region of the one conductivity type at a second device area, defining an insulated gate on the second device area, introducing impurities to form source and drain regions of the opposite conductivity type in the first well region, providing a layer doped with impurities of the opposite conductivity type on the first device area for forming an extrinsic base region, providing an insulating layer to cover the doped layer, forming an opening through the insulating and doped layers to expose a surface region of the first device area, and introducing through the opening impurities for forming an intrinsic base region of the opposite conductivity type and an emitter region of the one conductivity type within the intrinsic base region, characterised by forming the doped layer by providing a dopable layer on the first device area and then introducing the impurities to form the source and drain regions prior to providing the insulating layer, thereby doping the dopable layer with impurities of the opposite conductivity type, and by providing the insulating layer to cover the first and second device areas so that the insulating layer masks the second device area from the impurities for forming the intrinsic base and emitter regions.
Claim 2
Independent Claim
247 words
A method of manufacturing a semiconductor device comprising a bipolar transistor and an insulated gate field effect transistor, which method comprises providing a semiconductor body having, adjacent to one major surface, a collector region of one conductivity type at a first device area and a first well region of the one conductivity type at a second device area, defining an insulated gate on the second device area, introducing impurities to form source and drain regions of the opposite conductivity type in the first well region, providing a layer doped with impurities of the opposite conductivity type on the first device area for forming an extrinsic base region, providing an insulating layer to cover the doped layer, forming an opening through the insulating and doped layers to expose a surface region of the first device area, and introducing through the opening impurities for forming an intrinsic base region of the opposite conductivity type and an emitter region of the one conductivity type within the intrinsic base region, characterised by forming the doped layer by providing a dopable layer on the first device area and then introducing the impurities to form the source and drain regions prior to providing the insulating layer, thereby doping the dopable layer with impurities of the opposite conductivity type, and by providing the insulating layer to cover the first and second device areas so that the insulating layer masks the second device area from the impurities for forming the intrinsic base and emitter regions.
Claim 3
Dependent Claim
115 words
A method according to claim 1, further characterised by forming an insulated gate field effect transistor of complementary conductivity type by providing a second well region of the opposite conductivity type at a third device area adjacent to the one major surface, defining insulated gates on the second and third device areas, introducing impurities with the first and second device areas masked to form source and drain regions of the one conductivity type in the second well region prior to providing the insulating layer, and by providing the insulating layer to cover the third device area so as to mask the third device area from the impurities for forming the intrinsic base and emitter regions.
Claim 4
Dependent Claim
52 words
A method according to claim 2, further characterised by forming the opening by defining a first window through the insulating and doped layers, providing insulating regions on edges of the doped layer to form a second smaller window, and by introducing the impurities to form the emitter region via the second window.
Claim 5
Dependent Claim
22 words
A method according to claim 3, further characterised by introducing the impurities to form the intrinsic base region via the first window.
Claim 6
Dependent Claim
73 words
A method according to claim 4, further characterised by forming a relatively thin insulating layer covering the surface region and the edges of the doped layer exposed by the first window prior to introducing the opposite conductivity impurities for forming the intrinsic base region and causing impurities in the doped layer to diffuse into the semiconductor body for forming the extrinsic base region prior to introducing the impurities for forming the emitter region.
Claim 7
Dependent Claim
25 words
A method according to claim 5, further characterised by providing the insulating layer as an oxide layer with a covering of a flowable insulating layer.
Claim 8
Dependent Claim
20 words
A method according to claim 6, further characterised by providing the flowable insulating layer as a layer of borophosphosilicate glass.
Claim 9
Dependent Claim
26 words
A method according to claim 6, further characterised by forming the relatively thin oxide layer by causing the flowable layer to flow in an oxidising atmosphere.
Claim 10
Dependent Claim
56 words
A method according to claim 1, further characterised by also providing the dopable layer on a gate insulating layer and introducing impurities of the one conductivity type into the layer, with the part of the dopable layer on the first device area masked, to form the conductive gate layers of the insulating gate field effect transistor(s).
Claim 11
Independent Claim
21 words
A method according to any one of the preceding claims, further characterised by providing the dopable layer as a silicon layer.
Claim 12
Dependent Claim
33 words
A method according to claim 1, further characterised by introducing the impurities for forming the emitter region by implanting the impurities and then causing the introduced impurities to diffuse into the semiconductor body.
Claim 13
Dependent Claim
52 words
A method according to claim 1, further characterised by introducing the impurities for forming the emitter region by providing a further doped layer doped with impurities of the one conductivity type in the opening and then causing impurities to diffuse from the further doped layer into the semiconductor body via the opening.
Claim 14
Dependent Claim
49 words
A method according to claim 12, further characterised by opening contact holes for electrodes for the transistors through the further doped layer and the insulating layer, depositing and patterning conductive material to form the electrodes and then removing the portions of the further doped layer exposed between the electrodes.
Claim 15
Dependent Claim
52 words
A method according to claim 12, further characterized by forming the opening by defining a first window through the insulating and doped layers, providing insulating regions on edges of the doped layer to form a second smaller window, and by introducing the impurities to form the emitter region via the second window.
Claim 16
Dependent Claim
22 words
A method according to claim 14, further characterized by introducing the impurities to form the intrinsic base region via the first window.
Claim 17
Dependent Claim
75 words
A method according to claim 15, further characterized by forming a relatively thin insulating layer covering the surface region and the edges of the doped layer exposed by the first window prior to introducing the opposite conductivity impurities in the doped layer to intrinsic base region and causing impurities in the doped layer to diffuse into the semiconductor body for forming the extrinsic base region prior to introducing the impurities for forming the emitter region.
Claim 18
Dependent Claim
25 words
A method according to claim 1, further characterized by providing the insulating layer as an oxide layer with a covering of a flowable insulating layer.
Claim 19
Dependent Claim
20 words
A method according to claim 17, further characterized by providing the flowable insulating layer as a layer of borophosphosilicate glass.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-01-28 | 1994-07-30 | 1995-01-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-01-28 | 1998-07-30 | 1999-01-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-01-28 | 2002-07-30 | 2003-01-29 | $7700.00 | Window Closed / Lapsed |