US4987471A
Expired / Lapsed
US
⏱️ 0.0 years remaining
High-speed dielectrically isolated devices utilizing buried silicide regions
Assignee: Agere Systems LLC
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Filing: 1990-05-21
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Granted: 1991-01-22
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Expires: 2010-05-21
Abstract
Abstract A dielectrically-isolated structure and method of fabricating the same is disclosed wherein the structure includes a layer of silicide which is selectively doped, preferably using an ion implantation process. The doped silicide is then used as the diffusion source for the subsequent formation (through a heat treatment) of various active portions (collector, emitter, drain, source, for example) of a variety of high-voltage, high-speed active devices. The non-doped silicide is advantageously utilized as a low-resistance contact between the buried diffusion region and the surface electrode.
Inventors
- 👤 William G. Easter
- 👤 Anatoly Feygenson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 16:06
CPC Classifications
H; H10; H10P; H10P32/00; H10P32/10; H10P32/14; H10P32/1408; H10P32/1414; H10P32/17; H10P32/171; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/019; H10W10/10; H10W15/00; H10W15/01
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
94 words
A semiconductor device formed within a dielectrically isolated tub region of a silicon substrate, said tub region having sidewalls and a bottom surface said device comprising a silicide layer formed within said tub at the isolation boundary thereof, selected portions of said silicide layer being implanted with a dopant of a predetermined impurity; and at least one active region of said semiconductor device comprising a diffusion region formed by the migration of said implanted dopant from the silicide into the tub region and disposed adjacent to a selected doped portion of said silicide layer.
Claim 2
Dependent Claim
94 words
A semiconductor device formed within a dielectrically isolated tub region of a silicon substrate, said tub region having sidewalls and a bottom surface said device comprising a silicide layer formed within said tub at the isolation boundary thereof, selected portions of said silicide layer being implanted with a dopant of a predetermined impurity; and at least one active region of said semiconductor device comprising a diffusion region formed by the migration of said implanted dopant from the silicide into the tub region and disposed adjacent to a selected doped portion of said silicide layer.
Claim 3
Dependent Claim
51 words
A semiconductor device as defined in claim 1 wherein the silicide layer is formed to be completely contiguous with both the sidewalls and the bottom surface of the tub region, the at least one active region thus comprising a single diffusion region extending completely across the bottom surface of said tub.
Claim 4
Dependent Claim
22 words
A semiconductor device as defined in claim 2 wherein the single diffusion region comprises a collector portion of a laterial bipolar transistor.
Claim 5
Dependent Claim
23 words
A semiconductor device as defined in claim 2 wherein the single diffusion region comprises a gate portion of a junction field effect transistor.
Claim 6
Dependent Claim
25 words
A semiconductor device as defined in claim 2 wherein the single diffusion region comprises a channel portion of a lateral insulated gate field effect transistor.
Claim 7
Dependent Claim
64 words
A semiconductor device as defined in claim 1 wherein the silicide layer is formed to be silicide sidewalls completely contiguous with the sidewalls of the tub region, the at least one active region thus comprising a pair of diffusion regions, each diffusion region adjacent to a separate silicide sidewall, wherein each diffusion region is defined as a separate active portion of the semiconductor device.
Claim 8
Dependent Claim
52 words
A semiconductor device as defined in claim 6 wherein a first diffusion region of the pari of diffusion regions is defined as an emitter portion of a lateral bipolar transistor and the remaining diffusion region of said pair of diffusion regions is defined as a collector portion of said lateral bipolar transistor.
Claim 9
Dependent Claim
57 words
A semiconductor device as defined in claim 6 wherein a first diffusion region of the pair of diffusion regions is defined as a source portion of a lateral insulated gate field effect transistor and the remaining diffusion region of said pair of diffusion regions is defined as a drain portion of said insulated gate field effect transistor.
Claim 10
Dependent Claim
54 words
A semiconductor device as defined in claim 6 wherein a first diffusion region of the pair of diffusion regions is defined as a source portion of a junction field effect transistor and the remaining diffusion region of said pair of diffusion regions is defoned as a drain portion of said junction field effect transistor.
Claim 11
Dependent Claim
38 words
A semiconductor device as defined in claim 1 wherein the silicide layer is implanted with an n-type dopant so as to form selected regions of n-type silicide and at least one n-type active portion of the semiconductor device.
Claim 12
Dependent Claim
14 words
A semiconductor device as defined in claim 10 wherein the n-type dopant comprises phosphorus.
Claim 13
Dependent Claim
38 words
A semiconductor device as defined in claim 1 wherein the silicide layer is implanted with a p-type dopant so as to form selected regions of p-type silicide and at least one p-type active portion of the semiconductor device.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-01-21 | 1994-07-23 | 1995-01-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-01-21 | 1998-07-23 | 1999-01-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-01-21 | 2002-07-23 | 2003-01-22 | $7700.00 | Window Closed / Lapsed |