US4987092A
Expired / Lapsed
US
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Process for manufacturing stacked semiconductor devices
Assignee: Mitsubishi Electric Corp
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Filing: 1988-06-09
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Granted: 1991-01-22
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Expires: 2008-06-09
Abstract
Abstract An improved method of manufacturing semiconductor devices having a stacked structure is disclosed. A p-channel semiconductor substrate is prepared, and on the major surface of the substrate, n-channel source and drain regions and a gate electrode are formed to provide a n-channel transistor. Sidewalls are formed of P type single-crystal silicon on the opposite size of the gate electrode of n-channel transistor with an insulating layer interposed between the sidewalls and the gate electrode. A single-crystal layer covers the source, drain and gate electrode of the n-channel transistor and the sidewall structures. A P type impurity present in the sidewalls is diffused into the single-crystal layer.
Inventors
- 👤 Kiyoteru Kobayashi
- 👤 Tadashi Nishimura
- 👤 Hiroshi Morita
- 👤 Shuji Nakao
- 👤 Hidekazu Oda
- 👤 Yasuo Inoue
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 22:16
CPC Classifications
H; H10; H10B; H10B10/00; H10B10/12; H10B10/125; H10D; H10D84/00; H10D84/01; H10D84/02; H10D84/03; H10D84/038; H10D88/00; H10D88/01
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
383 words
A method for manufacturing semiconductor devices, comprising the steps of: preparing a semiconductor composite structure comprising a semiconductor substrate having a major surface and containing a predetermined concentration of an impurity of a first conductivity type; forming in said semiconductor at said major surface first and second impurity regions of a second conductivity type spaced apart from each other, a portion of said substrate between said first and second impurity regions of the second conductivity type defining a first channel region; forming a first insulating layer on said major surface of said substrate; forming a first conductor layer on said first insulating layer at a location above said first channel region coextensively therewith, said first conductor layer having a top surface and two side surfaces, and covering the first conductor layer by a second insulating layer; forming sidewalls on said two opposing side surfaces of said first conductor layer by covering the side surface with a second conductor layer containing an impurity of the first conductivity type with said second insulating layer interposed between said side surfaces and said second conductor layer; forming a third conductor layer to cover said first and second insulating layer and said sidewalls; and diffusing said impurity of the first conductivity type from within said sidewalls into said third conductor layer to form a pair of spaced apart impurity regions within said third conductor layers, whereby the region between said pair of spaced apart impurity regions within said third conductor layer forming a second channel region, wherein said step of forming said sidewalls of the first conductivity type with said second conductor layer comprises a step of forming said sidewalls of the first conductivity type with a first single-crystal conductor layer, wherein said first single-crystal conductor layer comprises a first single-crystal silicon layer, and wherein said step of forming said sidewall structures of the first conductivity type with said first single-crystal silicon layer comprises the steps of forming a second insulating layer on said top surface and said two side surfaces of said first conductor layer; forming a first polysilicon layer on said first and second insulating layers; converting said first polysilicon layer into a first single-crystal silicon layer of the first conductivity type; and etching away said first single-crystal silicon layer leaving said sidewalls as they are.
Claim 2
Independent Claim
383 words
A method for manufacturing semiconductor devices, comprising the steps of: preparing a semiconductor composite structure comprising a semiconductor substrate having a major surface and containing a predetermined concentration of an impurity of a first conductivity type; forming in said semiconductor at said major surface first and second impurity regions of a second conductivity type spaced apart from each other, a portion of said substrate between said first and second impurity regions of the second conductivity type defining a first channel region; forming a first insulating layer on said major surface of said substrate; forming a first conductor layer on said first insulating layer at a location above said first channel region coextensively therewith, said first conductor layer having a top surface and two side surfaces, and covering the first conductor layer by a second insulating layer; forming sidewalls on said two opposing side surfaces of said first conductor layer by covering the side surface with a second conductor layer containing an impurity of the first conductivity type with said second insulating layer interposed between said side surfaces and said second conductor layer; forming a third conductor layer to cover said first and second insulating layer and said sidewalls; and diffusing said impurity of the first conductivity type from within said sidewalls into said third conductor layer to form a pair of spaced apart impurity regions within said third conductor layers, whereby the region between said pair of spaced apart impurity regions within said third conductor layer forming a second channel region, wherein said step of forming said sidewalls of the first conductivity type with said second conductor layer comprises a step of forming said sidewalls of the first conductivity type with a first single-crystal conductor layer, wherein said first single-crystal conductor layer comprises a first single-crystal silicon layer, and wherein said step of forming said sidewall structures of the first conductivity type with said first single-crystal silicon layer comprises the steps of forming a second insulating layer on said top surface and said two side surfaces of said first conductor layer; forming a first polysilicon layer on said first and second insulating layers; converting said first polysilicon layer into a first single-crystal silicon layer of the first conductivity type; and etching away said first single-crystal silicon layer leaving said sidewalls as they are.
Claim 3
Dependent Claim
115 words
A method for manufacturing semiconductor devices according to claim 1, wherein; said step of converting said first polysilicon layer into said first single-crystal silicon layer of the first conductivity type comprises the steps of exposing at least a portion of said major surface of said semiconductor substrate by removing a portion of said first insulating layer at a location selected to be over either of said first and second impurity regions; converting said first polysilicon layer into an amorphous silicon layer; doping ions of the second conductivity type into said amorphous silicon layer; and growing a solid epitaxial layer, initiating the epitaxial layer from said exposed portion of said major surface of said semiconductor substrate.
Claim 4
Dependent Claim
36 words
A method for manufacturing semiconductor devices according to claim 2, wherein: said step of converting said first polysilicon layer into said amorphous silicon layer comprises a step of doping silicon ions into said first polysilicon layer.
Claim 5
Dependent Claim
29 words
A method for manufacturing semiconductor devices according to claim 1, wherein: said step of forming said third conductor layer comprises a step of forming a second single-crystal silicon layer.
Claim 6
Dependent Claim
39 words
A method for manufacturing semiconductor devices according to claim 4, wherein: said step of forming said second single-crystal silicon layer comprises a step of growing a solid epitaxial layer, initiating the epitaxial layer from said first single-crystal silicon layer.
Claim 7
Dependent Claim
70 words
A method for manufacturing semiconductor devices according to claim 5, wherein: said step of growing a solid epitaxial layer comprises the step of forming a second polysilicon layer over said first and second insulating layers on said substrate; and converting said second polysilicon layer into an amorphous layer by doping silicon ions into said second polysilicon layer; and subjecting said amorphous silicon layer to a heat treatment under predetermined conditions.
Claim 8
Dependent Claim
38 words
A method for manufacturing semiconductor devices according to claim 6, comprising the further step of: forming a resist over said second channel region and doping said impurity of said first conductivity type into said semiconductor substrate from above.
Claim 9
Dependent Claim
51 words
A method for manufacturing semiconductor devices according to claim 7, wherein: said composite semiconductor structure comprises a field effect transistor of the second conductivity type, said first conductor layer forming a gate electrode and said first and second impurity regions of the second conductivity type forming source and drain regions, respectively.
Claim 10
Dependent Claim
75 words
A method for manufacturing semiconductor devices according to claim 8, wherein: said pair of impurity regions of the first conductivity type within said third conductor layer form a source region and a drain region, respectively, and said first conductor layer forms a gate electrode whereby said pair of impurity regions of the first conductivity type within said third conductor layer and said first conductor layer comprises a field effect transistor of the first conductivity type.
Claim 11
Dependent Claim
34 words
A method for manufacturing semiconductor devices according to claim 9, wherein: said field effect transistor of the first conductivity type and said field effect transistor of the second conductivity type comprise a CMOS transistor.
Claim 12
Dependent Claim
18 words
A method for manufacturing semiconductor devices according to claim 10 wherein: said semiconductor composite structure includes a SRAM.
Claim 13
Dependent Claim
38 words
A method for manufacturing semiconductor devices according to claim 1, comprising the further step of: forming a resist over said second channel region and doping said impurity of said first conductivity type into said semiconductor substrate from above.
Claim 14
Dependent Claim
51 words
A method for manufacturing semiconductor devices according to claim 12, wherein: said composite semiconductor structure comprises a field effect transistor of the second conductivity type, said first conductor layer forming a gate electrode and said first and second impurity regions of the second conductivity type forming source and drain regions, respectively.
Claim 15
Dependent Claim
75 words
A method for manufacturing semiconductor devices according to claim 13, wherein: said pair of impurity regions of the first conductivity type within said third conductor layer form a source region and a drain region, respectively, and said first conductor layer forms a gate electrode whereby said pair of impurity regions of the first conductivity type within said third conductor layer and said first conductor layer comprise a field effect transistor of the first conductivity type.
Claim 16
Dependent Claim
34 words
A method for manufacturing semiconductor devices according to claim 14, wherein: said field effect transistor of the first conductivity type and said field effect transistor of the second conductivity type comprise a CMOS transistor.
Claim 17
Dependent Claim
18 words
A method for manufacturing semiconductor devices according to claim 15, wherein: said semiconductor composite structure includes a SRAM.
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