US4476475A
Expired / Lapsed
US
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Stacked MOS transistor
Assignee: Nortel Networks Technology Corp
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Filing: 1982-11-19
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Granted: 1984-10-09
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Expires: 2002-11-19
Abstract
Abstract In a stacked metal-oxide-semiconductor (SMOS) transistor, the transistor source, drain and channel each have a lower part formed in a silicon substrate and an upper part composed of recrystallized polysilicon. The device gate is located between the upper and lower channel parts. By vertically integrating a MOS transistor, performance limitations imposed by the direct scaling approach to device miniaturization are avoided.
Inventors
- 👤 Abdalla A. Naem
- 👤 Hussein M. Naguib
- 👤 Iain D. Calder
- 👤 Albert R. Boothroyd
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 03:56
CPC Classifications
H; H10; H10D; H10D88/00; H10D84/00; H10D84/01; H10D84/02; H10D84/03; H10D84/038; H10D88/01; H10P; H10P34/00; H10P34/40; H10P34/42
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
129 words
A transistor having first and second semiconductor layers separated by an insulated gate, the layers contacting one another at a first region laterally adjacent the insulated gate, at which first region both of the semiconductor layers are doped to form a source region, the layers contacting one another at a second region laterally adjacent the insulated gate at a position remote from the first region, at which second region both of the semiconductor layers are doped to form a drain region, the transistor having a first channel region extending between the source region and the drain region in the first semiconductor layer below the insulated gate, and a second channel region extending between the source region and the drain region in the second semiconductor layer above the insulated gate.
Claim 2
Dependent Claim
129 words
A transistor having first and second semiconductor layers separated by an insulated gate, the layers contacting one another at a first region laterally adjacent the insulated gate, at which first region both of the semiconductor layers are doped to form a source region, the layers contacting one another at a second region laterally adjacent the insulated gate at a position remote from the first region, at which second region both of the semiconductor layers are doped to form a drain region, the transistor having a first channel region extending between the source region and the drain region in the first semiconductor layer below the insulated gate, and a second channel region extending between the source region and the drain region in the second semiconductor layer above the insulated gate.
Claim 3
Dependent Claim
24 words
A transistor as claimed in claim 1 in which the first semiconductor layer is substrate silicon and the second semiconductor layer is recrystallized polysilicon.
Claim 4
Dependent Claim
22 words
A transistor as claimed in claim 1, in which the gate is insulated from the semiconductor layers by thermally grown silicon dioxide.
Claim 5
Dependent Claim
15 words
A transistor as claimed in claim 1, in which the gate is laser recrystallized polysilicon.
Claim 6
Dependent Claim
37 words
A transistor as claimed in claim 2, in which the recrystallized polysilicon in the second semiconductor layer at the source and drain regions has a crystal orientation forming an essentially epitaxial continuation of the first semiconductor layer.
References Cited (Backward Citations)
US4309224A
Cited
US4272880A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-10-09 | 1988-04-09 | 1988-10-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-10-09 | 1992-04-09 | 1992-10-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-10-09 | 1996-04-09 | 1996-10-09 | $7700.00 | Window Closed / Lapsed |