Two phase CMOS shift register bit for optimum power dissipation

Claim 1

A two-phase shift register bit apparatus having an input terminal for receiving bits of data, an output terminal for providing bits of data, power supply and ground terminals, comprising: first transfer means consisting of a single first MOS transistor having gate, first and second terminals, means coupling said first terminal of said first MOS transistor to said input terminal of said apparatus for receiving a first data bit in one of first and second mutually exclusive states, said gate terminal of said first MOS transistor being connected to receive a first clock signal, said first data bit being transferred to said second terminal when said first clock signal is received; first inverter having input and output terminals, said input terminal of said first inverter being connected only to said second terminal of said first MOS transistor, said input terminal of said first inverter being a dynamic storage node with respect to at least one state of said first data bit; first voltage pull means connected between said input and output terminals of said first inverter for providing a first pulled voltage at said second terminal of said first MOS transistor, said first voltage pull means consisting of a single third transistor having one of first and second mutually exclusive structures in accordance with whether said first MOS transistor is of the n-channel type or p-channel type, such that, in said first structure of said first voltage pull means, when said first data bit being in said first state, said first pulled voltage at said first inverter input terminal substantially equals the voltage at said power supply terminal, and such that, in said second structure of said first voltage pull means, when said first data bit being in said second state, said first pulled voltage at said first inverter input terminal substantially equals the voltage at said ground terminal; second transfer means consisting of a single second MOS transistor having gate, first and second terminals with the first terminal connected only to said output terminal of said first inverter for receiving from said output terminal of said first inverter a second data bit also in one of said first and second mutually exclusive states, said gate terminal of said second MOS transistor being connected to receive a second clock signal later in time than said first clock signal, said second data bit being received when said second clock signal is received; second inverter having input and output terminals, said input terminal of said second inverter being connected only to said second terminal of said second MOS transistor, said input terminal of said second inverter being a dynamic storage node with respect to at least one state of said second data bit; and second voltage pull means connected between said input and output terminals of said second inverter for providing a second pulled voltage at said second terminal of said second MOS transistor, said second voltage pull means consisting of a single fourth transistor also having one of said first and second mutually exclusive structures in accordance with whether said second MOS transistor is of the n-channel type or p-channel type, such that, in said first structure of said second voltage pull means, when said second data bit being in said first state, said second pulled voltage at said second inverter input terminal substantially equals the voltage at said power supply terminal, and such that, in said second structure of said second voltage pull means, when said second data bit being in said second state, said second pulled voltage at said second inverter input terminal substantially equals the voltage at said ground terminal.