Abstract A dynamic shift register circuit comprises an input terminal and an output terminal. It further comprises a first transfer gate circuit connected to the input terminal for receiving an input signal and transferring the input signal under the control of a first clock signal; an inverter circuit for inverting a level of an output signal of the first transfer gate circuit; a second transfer gate circuit connected to the inverter circuit for receiving an output signal of the inverter circuit and transferring the same under the control of a second clock signal which has a level opposite to that of the first clock signal; a signal follower circuit for producing an output signal having a level which follows a level of the output signal of the first transfer gate circuit; and a logic circuit connected to first and second power source voltages. The logic circuit is made operative by an output signal of the signal follower circuit and produces an inverter function at the output terminal, in response to an output signal of the second transfer gate circuit. The logic circuit comprises a capacitor element one terminal of which is connected to the output terminal of the signal follower circuit and the other terminal of which is connected to said output terminal of the dynamic shift register.
A dynamic shift register circuit comprising: an input terminal; an output terminal; first transfer gate means connected to the input terminal for receiving an input signal and transferring the input signal under the control of a first clock signal; inverter means for inverting the level of an output signal of the first transfer gate means; second transfer gate means connected to the inverter means for receiving an output signal of the inverter means and transferring the output signal of the inverter means under the control of a second clock signal which has a level opposite to that of the first clock signal; a signal follower circuit for producing an output signal having a level which follows the level of the output signal of the first transfer gate means; and a logic circuit connected to first and second power source voltages, comprising capacitive bootstrapping means connected between an output terminal of said signal follower circuit and an output terminal of the logic circuit, said logic circuit being made operative by an output signal of the signal follower circuit and producing an inverter function at the output terminal of the logic circuit, in response to an output signal of the second transfer gate means.
Claim 2
Dependent Claim
202 words
A dynamic shift register circuit comprising: an input terminal; an output terminal; first transfer gate means connected to the input terminal for receiving an input signal and transferring the input signal under the control of a first clock signal; inverter means for inverting the level of an output signal of the first transfer gate means; second transfer gate means connected to the inverter means for receiving an output signal of the inverter means and transferring the output signal of the inverter means under the control of a second clock signal which has a level opposite to that of the first clock signal; a signal follower circuit for producing an output signal having a level which follows the level of the output signal of the first transfer gate means; and a logic circuit connected to first and second power source voltages, comprising capacitive bootstrapping means connected between an output terminal of said signal follower circuit and an output terminal of the logic circuit, said logic circuit being made operative by an output signal of the signal follower circuit and producing an inverter function at the output terminal of the logic circuit, in response to an output signal of the second transfer gate means.
Claim 3
Dependent Claim
110 words
A dynamic shift register circuit according to claim 1, wherein said logic circuit comprises a first MOS transistor one terminal of which is connected to the first power source voltage, the other terminal of which is connected to said output terminal of the logic circuit and the gate of which is connected to the output terminal of the signal follower circuit, and a second MOS transistor one terminal of which is connected to the second power source voltage, the other terminal of which is connected to said output terminal of the logic circuit and the gate of which is connected to an output terminal of the second transfer gate means.
Claim 4
Dependent Claim
19 words
A dynamic shift register circuit according to claim 1, wherein said signal follower circuit is a source follower circuit.
Claim 5
Dependent Claim
60 words
A dynamic shift register circuit according to claim 2, wherein said capacitive bootstrapping means is comprised of a MOS transistor the gate of which is connected to the gate of the first MOS transistor and the output terminal of said signal follower circuit and the drain and source of which are connected to said output terminal of said logic circuit.