Monolithic bipolar convertible static shift register

Claim 2

A storage cell suitable for implementation as a monolithic static shift register for storing digital information comprising: a. semiconductor gating means, the gating means including first and second capacitors associated therewith, b. a data input terminal and a data output terminal connected to the semiconductor gating means, c. a charging line means connected to the first and second capacitors, the charging line means being adapted to receive a regeneration source for charging the first and second capacitors, d. the first capacitor being charged from a regeneration source, and selectively discharged in accordance with the digital level received at the data input terminal, e. the second capacitor being connected to the output terminal, the second capacitor being charged from the regeneration source, and selectively discharged in accordance with the charge stored on the first capacitor, the charge stored in the second capacitor being indicative of the digital state of the cell in accordance with the digital level received at the input terminal, and f. the semiconductor gating means further including a bipolar semiconductor switching transistor means connected between the first and second capacitors for maintaining the output terminal at a digital level in accordance with the digital level received at the input terminal so that the cell operates in a static mode, g. whereby the charging and discharging of said first and second capacitors comprise transient current flows.

Claim 3

A storage cell suitable for implementation as a monolithic static shift register for storing digital information as in claim 1 wherein: a. the semiconductor switching means comprises cross-coupled semiconductor flip-flop, and b. the charge stored on the second capacitor is effective to set the semiconductor flip-flop to either one of two conducting states for maintaining the output terminal at a digital level in accordance with the digital information received at the input terminal so that the cell operates in a static mode.

Claim 4

A storage cell suitable for implementation in monolithic form for storing digital information comprising: a. semiconductor gating means, the gating means including a first and a second capacitor associated therewith, b. a data input terminal and a data output terminal connected to the semiconductor gating means, c. a charging line means connected to the first and second capacitor, the charging line means being adapted to receive a regeneration source for charging the first and second capacitors, d. the first capacitor being charged from the regeneration source, and selectively discharged in accordance with the digital level received at the data input terminal, e. the second capacitor being connected to the output terminal, the second capacitor being charged from the regeneration source, and selectively discharged in accordance with the charge stored on the first capacitor, the charge stored on the second capacitor being indicative of the digital state of the cell in accordance with the information received at the input terminal, f. the semiconductor gating means further including a first bipolar semiconductor transistor device means having at least a first control terminal associated therewith, the first control terminal being connected to the second capacitor, and g. the first capacitor being periodically and selectively recharged from the regeneration source in accordance with the charge stored on the second capacitor in order to regenerate anew the charge stored on the second capacitor which is indicative of the digital state of the cell so that the storage cell operates in a static mode, h. whereby the charging and discharging of said first and second capacitors comprise transient current flows.

Claim 5

A storage cell suitable for implementation in monolithic form for storing digital information comprising: a. semiconductor gating means, the gating means including a first and a second capacitor associated therewith, b. a data input terminal and a data output terminal connected to the semiconductor gating means, c. a charging line means connected to the first and second capacitor, the charging line means being adapted to receive a regeneration source for charging the first and second capacitors, d. the first capacitor being charged from the regeneration source, and selectively discharged in accordance with the digital level received at the data input terminal, e. the second capacitor being connected to the output terminal, the second capacitor being charged from the regeneration source, and selectively discharged in accordance with the charge stored on the first capacitor, the charge stored on the second capacitor being indicative of the digital state of the cell in accordance with the information received at the input terminal, f. the semiconductor gating means further including a first bipolar semiconductor transistor device means having at least a first control terminal associated therewith, the first control terminal being connected to the second capacitor, and g. the first capacitor being periodically and selectively recharged from the regeneration source in accordance with the charge stored on the second capacitor in order to regenerate anew the charge stored on the second capacitor which is indicative of the digital state of the cell so that the storage cell operates in a static mode, h. whereby the charging and discharging of said first and second capacitors comprise transient current flows.

Claim 6

A storage cell suitable for implementation in monolithic form for storing digital information as in claim 3 wherein: a. the second capacitor is selectively and periodically recharged from the regeneration source in accordance with the first capacitor being periodically and selectively recharged in order to regenerate anew the charge stored on the second capacitor which is indicative of the digital state of the cell so that the storage cell operates in a static mode.

Claim 7

A storage cell suitable for implementation in monolithic form for storing digital information as in claim 4 wherein: a. the semiconductor gating means further comprises a second and a third semiconductor device means, b. the second semiconductor device means being connected to the data input terminal and to the first capacitor, the third semiconductor device means being connected to the first capacitor and to the second capacitor, c. the second semiconductor device means being rendered either nonconductive or conductive in accordance with either one or the other digital levels of information received at the data input terminal in order to selectively charge the first capacitor, d. the third semiconductor device means being rendered non-conductive or conductive in accordance with the charge stored on the first capacitor in order to selectively charge the second capacitor, the charge stored on the second capacitor being indicative of the digital state of the cell in accordance with the information received at the data input terminal, and the third semiconductor device means being periodically rendered nonconductive or conductive in accordance with the periodic recharging of the first capacitor in order to regenerate anew the charge stored on the second capacitor which is indicative of the digital state of the cell so that the storage cell operates in a static mode.

Claim 8

A storage cell suitable for implementation in monolithic form for storing digital information as in claim 5 wherein: a. the second and third semiconductor devices each further include a control terminal, each control terminal of the second and third semiconductor device means being adapted to receive an associated control signal, b. the second semiconductor device means being rendered nonconductive or conductive in response to its associated control signal and to one or the other digital levels received at the data input terminal in order to selectively charge the first capacitor by either maintaining the charge received from the regeneration source on the first capacitor or discharging the charge received from the regeneration source from the first capacitor, c. the third semiconductor device means being rendered nonconductive or conductive in accordance to its associated control signal and to the charge stored on the first capacitor in order to selectively charge the second capacitor by either maintaining the charge received from the regeneration source on the second capacitor or discharging the charge received from the regeneration source from the second capacitor, d. the first semiconductor device means being connected to the first capacitor and having a second control terminal, the second control terminal being adapted to receIve an associated control signal, e. the first semiconductor device means being periodically rendered nonconductive or conductive in accordance to its associated control signal and to the charge stored on the second capacitor in order to selectively and periodically recharge the first capacitor by either maintaining the charge received from the regeneration source on the first capacitor or discharging the charge received from the regeneration source from the first capacitor in order to regenerate anew the charge stored on the second capacitor which is indicative of the digital state of the cell so that the storage cell operates in a static mode.

Claim 9

A storage cell suitable for implementation in monolithic form for storing digital information as in claim 5 wherein: a. the second and third semiconductor device means are bipolar transistors, and b. the first and second capacitors are constituted by the parasitic base to collector capacitance of the second and third semiconductor device means bipolar transistors, respectively.

Claim 10

A storage cell suitable for implementation in monolithic form for storing digital information as in claim 7 wherein the cell is maintained in a operable static state solely in response to period non-dc signals.

Claim 11

A storage cell suitable for implementation in monolithic form for storing digital information as in claim 6 wherein: a. the second and third semiconductor device means are bipolar transistors, b. the first and second capacitors are constituted by the parasitic base to collector capacitance of the second and third semiconductor device means bipolar transistors, respectively, and c. the storage cell being maintained in an operable static state solely in response to periodic non-dc signals, d. the period non-dc signals comprising the regeneration source and the control signals associated with the first, second and third semiconductor device means.

Claim 12

A storage cell suitable for implementation in monolithic form for storing digital information as in claim 9 wherein: a. the charging line means comprises a first line connected to the first capacitor, the first line being adapted to initially receive a first regeneration signal source for selectively charging the first capacitor during a write mode and also to periodically receive the first regeneration source for recharging the first capacitor in order to regenerate anew the charge stored on the second capacitor during a static standby mode, and b. the charging line means further comprising a second line connected to the second capacitor, the second line being adapted to initially receive a second regeneration signal source for selectively charging the second capacitor during a write mode and also to periodically receive the second regeneration signal source for recharging the second capacitor in order to regenerate anew the charge stored on the second capacitor during a static standby mode.

Claim 13

A storage cell suitable for implementation in monolithic form for storing digital information as in Claim 10 wherein: a. the first line is connected in common to the control terminal associated with the second semiconductor device means, and b. second line is connected in common to the control terminal associated with the third semiconductor device means.

Claim 14

A storage cell suitable for implementation in monolithic form for storing digital information as in claim 11 wherein: a. the second and third semiconductor device means are bipolar transistors, and b. the first and second capacitors are constituted by the parasitic base to collector capacitance of the second and third semiconductor device means bipolar transistors, respectively.

Claim 15

A storage cell suitable for implementation in monolithic form for storing binary information as in claim 6 wherein: a. the second capacitor is selectively and periodically recharged from the regeneration source in accordance with the first capacitor being selectively and perioDically recharged in order to regenerate anew the charge stored on the second capacitor which is indicative of the digital state of the cell so that the storage cell operates in a static mode.