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US4984052A Expired / Lapsed US ⏱️ 0.0 years remaining

Bonded substrate of semiconductor elements having a high withstand voltage

Assignee: Toshiba Corp
•
Filing: 1989-10-10
•
Granted: 1991-01-08
•
Expires: 2009-10-10
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Abstract

Abstract A bonded substrate comprises a first semiconductor substrate in which a plurality of semiconductor elements are formed, a second semiconductor substrate adhered to the first semiconductor substrate so as to support it by means of an insulating layer interposed therebetween, a first semi-insulating polysilicon layer interposed between the first semiconductor substrate and the insulating layer, and a second semi-insulating polysilicon layer interposed between the insulating layer and the second semiconductor substrate. The semi-insulating polysilicon layers serve to reduce the voltage applied to the insulating layer and to prevent the insulating layer from being etched.

Inventors

  • 👤 Yutaka Koshino
  • 👤 Yoshiro Baba
  • 👤 Akihiko Osawa
  • 👤 Satoshi Yanagiya

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-27 14:45
CPC Classifications
H; H10; H10P; H10P90/00; H10P90/19; H10P90/1904; H10P90/1906; H10W; H10W10/00; H10W10/01; H10W10/041; H10W10/061; H10W10/10; H10W10/181; H10W10/40; H10P90/1914; H10W10/011; H10W10/012; H10W10/13; Y; Y10; Y10S; Y10S257/00; Y10S257/914

Claims Analysis

Total Claims: 7
Claim 1
Independent Claim 129 words
A bonded substrate of semiconductor elements having a high withstand voltage, comprising: a first semiconductor substrate having a plurality of semiconductor elements disposed therein and thereon; a second semiconductor substrate bonded to a rear surface of the first semiconductor substrate with a first insulating layer provided therebetween; a first semi-insulating polysilicon layer provided between said first semiconductor substrate and said first insulating layer; a second semi-insulating polysilicon layer provided between said second semiconductor substrate and said first insulating layer; a trench formed in the first semiconductor substrate and extending through the first semiconductor substrate to the first semi-insulating polysilicon layer; a second insulating layer provided on an inner wall of the trench; and a polysilicon layer provided on the second insulating layer covering the inner wall of the trench.
Claim 2
Dependent Claim 129 words
A bonded substrate of semiconductor elements having a high withstand voltage, comprising: a first semiconductor substrate having a plurality of semiconductor elements disposed therein and thereon; a second semiconductor substrate bonded to a rear surface of the first semiconductor substrate with a first insulating layer provided therebetween; a first semi-insulating polysilicon layer provided between said first semiconductor substrate and said first insulating layer; a second semi-insulating polysilicon layer provided between said second semiconductor substrate and said first insulating layer; a trench formed in the first semiconductor substrate and extending through the first semiconductor substrate to the first semi-insulating polysilicon layer; a second insulating layer provided on an inner wall of the trench; and a polysilicon layer provided on the second insulating layer covering the inner wall of the trench.
Claim 3
Dependent Claim 19 words
The bonded substrate according to claim 1, wherein said first and second semiconductor substrates are each formed of silicon.
Claim 4
Dependent Claim 18 words
The bonded substrate according to claim 1, wherein said insulating layer is formed of an SiO 2 layer.
Claim 5
Dependent Claim 22 words
The bonded substrate according to claim 1, wherein said first insulating layer is an SiO 2 layer containing boron as an impurity.
Claim 6
Dependent Claim 20 words
The bonded substrate according to claim 1, wherein said insulating layer is formed of a phosphorous doped SiO 2 layer.
Claim 7
Dependent Claim 20 words
The bonded substrate according to claim 1, wherein said insulating layer is formed of an arsenic doped SiO 2 layer.

References Cited (Backward Citations)

US3990102A Cited
US4131910A Cited
US4242697A Cited
JPS59110132A Cited
US4611386A Cited
US4755863A Cited
US4792834A Cited
US4710794A Cited
US4924284A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1994-01-07 1994-07-09 1995-01-08 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1998-01-07 1998-07-09 1999-01-08 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2002-01-07 2002-07-09 2003-01-08 $7700.00 Window Closed / Lapsed

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