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US4975757A Expired / Lapsed US ⏱️ 0.0 years remaining

Complementary semiconductor device

Assignee: Toshiba Corp
•
Filing: 1987-10-20
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Granted: 1990-12-04
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Expires: 2007-10-20
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Abstract

Abstract A complementary semiconductor device includes P- and N-type semiconductor regions separately formed in a semiconductor substrate and having substantially the same concentration of impurities. N-and P-channel type silicon gate field effect transistors are formed in the P-and N-channel type regions, respectively. Gate electrodes of the P-and N-channel type silicon gate field effect transistors are formed by polycrystalline silicons of the same conductivity type. An impurity of the same conductivity type is doped into both the semiconductor regions to provide channel doped regions.

Inventors

  • 👤 Hideharu Egawa
  • 👤 Koji Matsuki
  • 👤 Yasoji Suzuki

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-29 06:51
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/0167; H10D84/02; H10D84/03; H10D84/038; H10D84/80; H10D84/82; H10D84/83; H10D84/85; H10D84/859

Claims Analysis

Total Claims: 7
Claim 1
Independent Claim 128 words
A complementary semiconductor device comprising: a semiconductor substrate of one conductivity type having a low impurity concentration; non-abutting P- and N-type semiconductor regions formed in said substrate and having an impurity concentration higher than that of said substrate; an N-channel type silicon gate field effect transistor including source and drain regions formed in said P-type semiconductor region, and a gate region including a gate electrode comprising a polycrystalline silicon layer of one conductivity type; and a P-channel type silicon gate field effect transistor including source and drain regions formed in said N-type semiconductor region, and a gate region including a gate electrode comprising a polycrystalline silicon layer; wherein said P- and N-type semiconductor regions are physically separated apart from each other by a portion of said semiconductor substrate.
Claim 2
Dependent Claim 128 words
A complementary semiconductor device comprising: a semiconductor substrate of one conductivity type having a low impurity concentration; non-abutting P- and N-type semiconductor regions formed in said substrate and having an impurity concentration higher than that of said substrate; an N-channel type silicon gate field effect transistor including source and drain regions formed in said P-type semiconductor region, and a gate region including a gate electrode comprising a polycrystalline silicon layer of one conductivity type; and a P-channel type silicon gate field effect transistor including source and drain regions formed in said N-type semiconductor region, and a gate region including a gate electrode comprising a polycrystalline silicon layer; wherein said P- and N-type semiconductor regions are physically separated apart from each other by a portion of said semiconductor substrate.
Claim 3
Dependent Claim 23 words
A complementary semiconductor device according to claim 1, in which the gate regions include an oxide layer formed under the polycrystalline silicon layer.
Claim 4
Dependent Claim 27 words
A complementary semiconductor device according to claim 2, in which said semiconductor substrate has an impurity concentration of about 10 13 to 10 14 atoms/cm 3 .
Claim 5
Dependent Claim 27 words
A complementary semiconductor device according to claim 3, in which said P- and N-type semiconductor regions have an impurity concentration of about 10 15 atoms/cm 3 .
Claim 6
Dependent Claim 19 words
A complementary semiconductor device according to claim 1 in which the polycrystalline silicon layers are of an N-conductivity type.
Claim 7
Dependent Claim 19 words
A complementary semiconductor device according to claim 1 in which the polycrystalline silicon layers are of a P-conductivity type.

References Cited (Backward Citations)

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USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1993-12-03 1994-06-04 1994-12-04 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1997-12-03 1998-06-04 1998-12-04 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2001-12-03 2002-06-04 2002-12-04 $7700.00 Window Closed / Lapsed

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