Bus arbiter with equitable priority scheme

Claim 1

A bus arbiter for a computer system comprising a plurality of processors coupled to a bus to which at least one of said processors requests access by generating a bus request signal, each of said plurality of processors having associated therewith a processor number, said bus arbiter comprising: clock means for generating a clock signal, said clock means comprising; a first gate responsive to said bus request signal and generating a first output signal; first logic means responsive to said bus request signal, to a delayed clock signal, and to a bus grant signal for generating a second output signal; a second gate responsive to said first and second output signals and generating said clock signal; signal delay means responsive to said clock signal for generating said delayed clock signal; second logic means for generating a count signal representing a number of a processor being given priority; latch means responsive to said bus request signal and to said clock signal for generating a latched bus request signal; and bus grant means responsive to said latched bus request signal and to said count signal for generating said bus grant signal, permitting one of said access-requesting processors to access said bus.