Memory port priority access system with inhibition of low priority lock-out

Claim 1

Apparatus for handling multiple memory requests for access to a memory bank, the request originating in a plurality of different processors and at random times in relation to each other, the requests identifying the need for data communication between the respective processor and the memory bank, each request signal accompanied by addressing signals, the processor including at least one central processing unit and one input/output processor requesting memory access independently from each other, comprising: timing means providing timing signals on a cyclically repetitive basis and in synchronism with memory access cycles; first means including a plurality of storage devices respectively associated with the processors of the plurality and connected for receiving memory request signals and storing same; gating means connected to the timing means and operatively connected to pass the request signals respectively to the storage devices of the first means, concurrently and in synchronism with a timing signal representative of an instant close to the end of a memory cycle; first circuit means connected for enabling the gating means when none of the plurality of storage devices has no longer stored a request signal; second circuit means connected for processing the memory access requests as identified by request signals stored in the storage device of the plurality in predetermined priority, one memory cycle per request, and including circuit means connected to the storage devices to erase a stored request signal identifying a request that is processed in a memory cycle, during that memory cycle, prior to the particular instant within that cycle; and third circuit means connected additionally to the gating means for rendering storage of a request dependent upon the presence of the particular memory location in the bank as identified by the addressing signals and to which access is requested by the respective request signal.