US4972189A
Expired / Lapsed
US
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Correction for DC offset in A/D converters
Assignee: Grumman Corp
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Filing: 1989-10-23
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Granted: 1990-11-20
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Expires: 2009-10-23
Abstract
Abstract A means for correction for DC offset in an analog-to-digital converter which utilizes a hardware implemented iterative digital integration process. During the off time of an analog-to-digital converter thermal noise is digitized by the analog-to-digital converter and a specific number of least significant bits which are sufficient to handle the thermal noise levels are accumulated for a given number of samples. The accumulated sum of thermal noise samples is then converted into an analog signal and scaled by the number of samples taken so as to effectively find the average value from the sample collected. This scaled analog signal is then added to the thermal noise input signal wherein the process is repeated a predetermined number of times. Upon completion of the last iteration, the scaled analog signal which is representative of the DC offset inherent in the particular analog-to-digital converter is added to the true analog signal to be digitized.
Inventors
- 👤 Bruno Polito
- 👤 Juan Adrover
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 14:19
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/10; H03M1/1009; H03M1/1014; H03M1/1023; H03M1/12
Claims Analysis
Total Claims: 27
Claim 1
Independent Claim
154 words
A means for correction for DC offset in an analog-to-digital converter when said analog-to-digital converter is not needed for signal conversion, said means comprising: (a) a switching means operable to switch said means for correction between correction mode of operating and a normal operation mode; (b) an accumulating means for the digital accumulation of a predetermined number of least significant bits from an n-bit output of said analog-to-digital converter when said switching means switches said means for correction into said correction mode of operation which results in an m-bit sum accumulated for a predetermined number of samples, a counter means being operable to maintain said predetermined number of samples; (c) an accumulating digital-to-analog converter which converts said m-bit sum from said accumulating means into an analog correction signal; and (d) an inversion means which inverts the polarity of said analog correction signal from said accumulating digital-to-analog converter to derive a DC offset correction signal.
Claim 2
Dependent Claim
154 words
A means for correction for DC offset in an analog-to-digital converter when said analog-to-digital converter is not needed for signal conversion, said means comprising: (a) a switching means operable to switch said means for correction between correction mode of operating and a normal operation mode; (b) an accumulating means for the digital accumulation of a predetermined number of least significant bits from an n-bit output of said analog-to-digital converter when said switching means switches said means for correction into said correction mode of operation which results in an m-bit sum accumulated for a predetermined number of samples, a counter means being operable to maintain said predetermined number of samples; (c) an accumulating digital-to-analog converter which converts said m-bit sum from said accumulating means into an analog correction signal; and (d) an inversion means which inverts the polarity of said analog correction signal from said accumulating digital-to-analog converter to derive a DC offset correction signal.
Claim 3
Dependent Claim
176 words
The means for correction for DC offset according to claim 1 wherein said switching means comprises: (a) a first switching means operable to switch between a signal input position and a grounded input position, said switching means having an output connected to a summing means; (b) a second switching means operable to switch an n-bit output of said analog-to-digital converter between an output mode position and a calibration mode position; (c) an accumulating means for the digital accumulation of a predetermined number of least significant bits from said n-bit output of said analog-to-digital converter when said switching means is in the calibration mode position, which results in an m-bit sum; (d) a counter means operable to maintain a count of a predetermined number of samples being accumulated by said accumulating means; (e) an accumulating digital-to-analog converter which converts said m-bit sum from said accumulating means into an analog correction signal; and (f) an inversion means which inverts the polarity of said analog correction signal from said accumulating digital-to-analog converter to derive a DC offset correction signal.
Claim 4
Dependent Claim
34 words
The means for correction for DC offset according to claim 2 wherein said first switching means switches between said signal input position and said grounded input position upon receipt of a calibrate control signal.
Claim 5
Dependent Claim
56 words
The means for correction for DC offset according to claim 3 wherein said first switching means selects an analog input signal for said analog-to-digital converter when said switching means is in said signal input position and selects a thermal noise calibrate signal for said analog-to-digital converter when said switching means is in said grounded input position.
Claim 6
Dependent Claim
25 words
The means for correction for DC offset according to claim 4 wherein said first switching means is a controllable single pole, double throw analog switch.
Claim 7
Dependent Claim
34 words
The means for correction for DC offset according to claim 4 wherein said second switching means switches between said output mode position and said calibration mode position upon receipt of said calibrate control signal.
Claim 8
Dependent Claim
67 words
The means for correction for DC offset according to claim 6 wherein said second switching means diverts said n-bit output of said analog-to-digital converter to a processing means when said second switching means is in said output mode position and diverts said predetermined number of least significant bits from said n-bit output to said accumulating means when said second switching means is in said calibration mode position.
Claim 9
Dependent Claim
20 words
The means for correction for DC offset according to claim 7 wherein said second switching means is a digital switch.
Claim 10
Dependent Claim
77 words
The means for correction for DC offset according to claim 7 wherein said accumulating means is a m-bit accumulator operable for summing said predetermined number of samples of said predetermined number of least significant bits in a predetermined sampling period resulting in said m-bit sum, said m-bit accumulator is synchronized with said analog-to-digital converter by means of a timing pulse supplied from a system clock, said system clock running at the same rate as said analog-to-digital converter.
Claim 11
Dependent Claim
63 words
The means for correction for DC offset according to claim 9 wherein said counter means is synchronized with said m-bit accumulator by means of said timing pulse supplied from said system clock, said counter means is a p-bit synchronous counter whereupon reaching a count equal to said predetermined number of samples said p-bit synchronous counter sends a shift pulse to said m-bit accumulator.
Claim 12
Dependent Claim
35 words
The means for correction for DC offset according to claim 10 wherein said m-bit accumulator shifts said m-bit sum to said accumulating digital-to-analog converter upon receipt of said shift pulse from said p-bit synchronous counter.
Claim 13
Dependent Claim
42 words
The means for correction for DC offset according to claim 11 wherein said accumulating digital-to-analog converter converts said m-bit sum at the end of said sampling period, said accumulating digital-to-analog converter accumulates said m-bit sum for a predetermined number of sampling periods.
Claim 14
Dependent Claim
67 words
The means for correction for DC offset according to claim 12 wherein said inversion means is an inverting amplifier, said inverting amplifier has a gain, G, given by G=-R.sub.f /R.sub.i, where R f is a feedback resistance and R i is an input resistance, said gain is selected to be equal to one over the predetermined number of samples of said predetermined number of least significant bits.
Claim 15
Dependent Claim
28 words
The means for correction for DC offset according to claim 13 wherein said inverting amplifier with gain G outputs said DC offset correction signal to said summing means.
Claim 16
Dependent Claim
39 words
The means for correction for DC offset according to claim 14 wherein said summing means adds said DC offset correction signal to said output of said analog switch, said summing means outputs a sum signal to said analog-to-digital converter.
Claim 17
Dependent Claim
26 words
The means for correction for DC offset according to claim 15 wherein said sum signal is a DC offset corrected analog input signal to be digitized.
Claim 18
Dependent Claim
24 words
The means for correction for DC offset according to claim 16 wherein said sum signal is a DC offset corrected thermal noise calibration signal.
Claim 19
Dependent Claim
101 words
A digital integration method for fast, continuous correction for DC offset in an analog-to-digital converter during analog-to-digital converter off time, said method comprising the step of: (a) switching a thermal noise grounded input signal into said analog-to-digital converter; (b) switching a n-bit output of said analog-to-digital converter to a m-bit accumulator; (c) accumulating a predetermined number of least significant bits from said n-bit output of said analog-to-digital converter resulting in a m-bit sum; (d) converting said m-bit sum into an analog correction signal; and (e) inverting the polarity of said analog correction signal which results in a DC offset correction signal
Claim 20
Dependent Claim
101 words
A digital integration method for fast, continuous correction for DC offset in an analog-to-digital converter during analog-to-digital converter off time, said method comprising the step of: (a) switching a thermal noise grounded input signal into said analog-to-digital converter; (b) switching a n-bit output of said analog-to-digital converter to a m-bit accumulator; (c) accumulating a predetermined number of least significant bits from said n-bit output of said analog-to-digital converter resulting in a m-bit sum; (d) converting said m-bit sum into an analog correction signal; and (e) inverting the polarity of said analog correction signal which results in a DC offset correction signal
Claim 21
Dependent Claim
39 words
The method for fast, continuous correction according to claim 18 wherein said fast, continuous correction further includes the step of adding said DC offset correction signal to said thermal noise grounded input signal as part of an iterative cycle.
Claim 22
Dependent Claim
40 words
The method for fast, continuous correction according to claim 19 ,wherein said fast, continuous correction still further includes the step of adding said DC offset correction signal to an analog signal to be digitized upon completion of said iterative cycle.
Claim 23
Dependent Claim
34 words
The method for fast, continuous correction according to claim 20 wherein said step of switching said thermal grounded input signal into said analog-to-digital converter is accomplished by the reception of a calibrate control signal.
Claim 24
Dependent Claim
36 words
The method for fast, continuous correction according to claim 21 wherein said step of switching said n-bit output of said analog-to-digital converter to said m-bit accumulator is accomplished by the reception of said calibrate control signal.
Claim 25
Dependent Claim
87 words
The method for fast, continuous correction according to claim 22 wherein said step of accumulating a predetermined number of least significant bits includes the steps of: (a) summing a predetermined number of samples of said predetermined number of least significant bits in a predetermined sampling period resulting in said m-bit sum; (b) counting said predetermined number of samples being accumulated by said m-bit accumulator utilizing a counter; and (c) shifting said m-bit sum into an accumulating digital-to-analog converter upon receipt of a shift pulse from said counter.
Claim 26
Dependent Claim
47 words
The method for fast, continuous correction according to claim 23 wherein said step of converting said m-bit sum into an analog correction signal includes accumulating a plurality of m-bit sums as part of said iterative cycle and subsequently converting an accumulated sum into said analog correction signal.
Claim 27
Dependent Claim
35 words
The method for fast, continuous correction according to claim 24 wherein said step of inverting the polarity of said analog correction signal further includes dividing said analog correction signal by said predetermined number of samples.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-11-19 | 1994-05-21 | 1994-11-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-11-19 | 1998-05-21 | 1998-11-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-11-19 | 2002-05-21 | 2002-11-20 | $7700.00 | Window Closed / Lapsed |