US4140925A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Automatic d-c offset cancellation in PCM encoders
Assignee: Nortel Networks Ltd
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Filing: 1977-07-15
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Granted: 1979-02-20
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Expires: 1997-07-15
Abstract
Abstract During encoding of voice frequency (VF) signal in a PCM channel bank the encoder encounters direct current (d-c) offset component resulting from the particular VF signal. Such d-c offsets cause errors above and beyond the normal errors inherent in the normal encoding process. The present invention alleviates this problem by providing an automatic d-c offset cancellation circuit which closely follows the d-c offset component and provides a d-c component of opposite sign to cancel it.
Inventors
- 👤 Fred Meyer
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 04:35
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/12; H03M1/124; H03M1/129; H03M1/1295
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
170 words
An automatic d-c offset cancellation circuit for a pulse code modulation (PCM) encoder including a comparator at its output, comprising: a capacitor for charge storage, coupled to an input of said comparator by means of a unity gain buffer amplifier; first and second transistors for charging said capacitor, said first transistor an NPN transistor responding to a first control signal to charge said capacitor negatively; said second transistor a PNP transistor responding to a second control signal to charge said capacitor positively; first and second flip-flops and first and second OR gates for controlling said first and second transistors, said first flip-flop responsive to the output signal of said comparator; said second flip-flop responsive to an enable signal; said first OR gate responsive to the standard output signal of each flip-flop, said second OR gate responsive to the complementary output signal of said first flip-flop and the output signal of said second flip-flop; the output signals of said OR gates being said control signals for said first and second transistors.
Claim 2
Dependent Claim
170 words
An automatic d-c offset cancellation circuit for a pulse code modulation (PCM) encoder including a comparator at its output, comprising: a capacitor for charge storage, coupled to an input of said comparator by means of a unity gain buffer amplifier; first and second transistors for charging said capacitor, said first transistor an NPN transistor responding to a first control signal to charge said capacitor negatively; said second transistor a PNP transistor responding to a second control signal to charge said capacitor positively; first and second flip-flops and first and second OR gates for controlling said first and second transistors, said first flip-flop responsive to the output signal of said comparator; said second flip-flop responsive to an enable signal; said first OR gate responsive to the standard output signal of each flip-flop, said second OR gate responsive to the complementary output signal of said first flip-flop and the output signal of said second flip-flop; the output signals of said OR gates being said control signals for said first and second transistors.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1982-02-19 | 1982-08-21 | 1983-02-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1986-02-19 | 1986-08-21 | 1987-02-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1990-02-19 | 1990-08-21 | 1991-02-20 | $7700.00 | Window Closed / Lapsed |