US4193066A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Automatic bias adjustment circuit for a successive ranged analog/digital converter
Assignee: United States Department of the Air Force
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Filing: 1978-04-20
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Granted: 1980-03-11
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Expires: 1998-04-20
Abstract
Abstract An automatic bias adjustment circuit for a successive ranged analog/digital converter (SRADC) that eliminates the need for manual bias adjustments and calibration inputs. The bias correction circuit comprehends dual flip flops that are triggered by selected comparators of the SRADC n bit parallel analog/digital converter. The flip flop output signals control up/down counters whose output bits drive digital/analog converter. The digital/analog converted signals are introduced back into the SRADC analog chain to zero bias errors in a particular sub-range. A disabling circuit prevents operation of the bias adjustment circuits for the first sub-range.
Inventors
- 👤 Steven Morrison
- 👤 Thomas K. Lisle, Jr.
- 👤 Clarence C. Glover
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 22:53
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/10; H03M1/1009; H03M1/1014
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
205 words
In a successive ranged analog/digital converter having a switchable gain amplifier chain and an n bit parallel analog/digital converter, the improvement of an automatic bias adjustment circuit, said automatic bias adjustment circuit comprising up/down counter means, digital/analog converter means driven by said up/down counter means and providing bias correction signals in response thereto, said bias correction signals being fed to said switchable gain amplifier chain, a logic circuit for developing from said n bit parallel analog/digital converter first and second logic functions, said logic functions defining a given sub-range, up/down counter actuating means receiving said first and second logic functions and clock signals, said actuating means enabling said up/down counter means in response to said first logic function and effecting counting thereby in a direction dictated by the state of said second logic function, disabling means for disabling said up/down counter actuating means in response to logic functions defining the first sub-range of said successive ranged analog/digital converter, said disabling means comprising a dual input OR gate connected to receive logic function inputs from said n bit parallel analog/digital converter, and a flip flop circuit receiving the output of said OR gate and a clock signal and providing an output disabling signal in response thereto.
Claim 2
Dependent Claim
205 words
In a successive ranged analog/digital converter having a switchable gain amplifier chain and an n bit parallel analog/digital converter, the improvement of an automatic bias adjustment circuit, said automatic bias adjustment circuit comprising up/down counter means, digital/analog converter means driven by said up/down counter means and providing bias correction signals in response thereto, said bias correction signals being fed to said switchable gain amplifier chain, a logic circuit for developing from said n bit parallel analog/digital converter first and second logic functions, said logic functions defining a given sub-range, up/down counter actuating means receiving said first and second logic functions and clock signals, said actuating means enabling said up/down counter means in response to said first logic function and effecting counting thereby in a direction dictated by the state of said second logic function, disabling means for disabling said up/down counter actuating means in response to logic functions defining the first sub-range of said successive ranged analog/digital converter, said disabling means comprising a dual input OR gate connected to receive logic function inputs from said n bit parallel analog/digital converter, and a flip flop circuit receiving the output of said OR gate and a clock signal and providing an output disabling signal in response thereto.
Claim 3
Dependent Claim
21 words
An automatic bias adjustment circuit as defined in claim 1 wherein said up/down counter means comprises first an second up/down counters,
Claim 4
Dependent Claim
183 words
said digital/analog converter means comprises a first digital/analog converter connected to receive the output of said first up/down counter and a second digital/analog converter connected to receive the output of said second up/down counter, said up/down counter actuating means comprises a first dual flip flop circuit having first and second outputs connected to said first up/down counter and a first input connected to receive logic function inputs from said n bit parallel analog/digital converter and a second dual flip flop circuit having first and second outputs connected to said second up/down counter and a first input connected to receive logic functions from said n bit parallel analog/digital converter, and said logic circuit comprises first and second dual input NOR gates, said first NOR gate having one input connected to the output of said disabling means, the other input connected to the output of said second NOR gate and its output connected to the second inputs of said dual flip flop circuits, and said second NOR gate having its inputs connected to receive logic function input signals from said n bit parallel analog/digital converter.
Claim 5
Dependent Claim
183 words
said digital/analog converter means comprises a first digital/analog converter connected to receive the output of said first up/down counter and a second digital/analog converter connected to receive the output of said second up/down counter, said up/down counter actuating means comprises a first dual flip flop circuit having first and second outputs connected to said first up/down counter and a first input connected to receive logic function inputs from said n bit parallel analog/digital converter and a second dual flip flop circuit having first and second outputs connected to said second up/down counter and a first input connected to receive logic functions from said n bit parallel analog/digital converter, and said logic circuit comprises first and second dual input NOR gates, said first NOR gate having one input connected to the output of said disabling means, the other input connected to the output of said second NOR gate and its output connected to the second inputs of said dual flip flop circuits, and said second NOR gate having its inputs connected to receive logic function input signals from said n bit parallel analog/digital converter.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1983-03-11 | 1983-09-10 | 1984-03-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1987-03-11 | 1987-09-10 | 1988-03-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1991-03-11 | 1991-09-10 | 1992-03-11 | $7700.00 | Window Closed / Lapsed |