Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
177 words
A zero reference and offset compensation circuit adapted to compensate for zero reference and offset errors in an operational amplifier operating in the inverting mode, comprising: comparison means for comparing the zero condition signal output of said operational amplifier with representations of lower and upper boundary signal levels; a pair of digital-to-analog converters having their respective analog outputs connected through appropriate scaling networks to the inverting input terminal and to the non-inverting input terminal of said operational amplifier to correct, respectively, for current drift and voltage drift; means connected to the output of said comparison means for generating an incremented digital signal whenever said comparison means indicates said zero condition signal output exceeds either boundary signal level, said incremented digital signal being incremented either up or down to drive an associated D/A converter either up or down to bring said zero condition signal within the boundary which has been exceeded; and means for selectively connecting the output of said means for generating an incremented digital signal with one or the other of said pair of digital-to-analog converters.
Claim 2
Dependent Claim
177 words
A zero reference and offset compensation circuit adapted to compensate for zero reference and offset errors in an operational amplifier operating in the inverting mode, comprising: comparison means for comparing the zero condition signal output of said operational amplifier with representations of lower and upper boundary signal levels; a pair of digital-to-analog converters having their respective analog outputs connected through appropriate scaling networks to the inverting input terminal and to the non-inverting input terminal of said operational amplifier to correct, respectively, for current drift and voltage drift; means connected to the output of said comparison means for generating an incremented digital signal whenever said comparison means indicates said zero condition signal output exceeds either boundary signal level, said incremented digital signal being incremented either up or down to drive an associated D/A converter either up or down to bring said zero condition signal within the boundary which has been exceeded; and means for selectively connecting the output of said means for generating an incremented digital signal with one or the other of said pair of digital-to-analog converters.
Claim 3
Dependent Claim
72 words
A zero reference and offset compensation circuit as set out in claim 1 in combination with a set-reset latch to activate said means for generating an incremented digital signal when said operational amplifier is not processing an analog signal and to deactivate said means for generating an incremented digital signal when said comparison means indicates said zero condition signal output does not exceed said representation of lower and upper boundary signal levels.
Claim 4
Dependent Claim
82 words
A zero reference and compensation circuit as set out in claim 2 wherein said means for generating an incremented digital signal comprises an oscillator, an AND gate whose inputs are connected, respectively, to the output of said comparison means and to the output of said oscillator and to the Q line from said set-reset latch, and an up/down binary counter whose inputs are connected, respectively, to the output of said AND gate and to a logic state line from said comparison means.
Claim 5
Dependent Claim
24 words
A zero reference and compensation circuit as set out in claim 1 wherein said means for generating an incremented digital signal comprises a microprocessor.
Claim 6
Dependent Claim
57 words
A zero reference and compensation circuit in accordance with claim 4 wherein said means for selectively connecting the output of said means for generating an incremented digital signal with one or the other of said pair of digital-to-analog converters is incorporated within said microprocessor and is activated by a current range select line input to said microprocessor.
Claim 7
Dependent Claim
38 words
A zero reference and compensation circuit in accordance with claim 5 in combination with switching means across the inverting terminal of said operational amplifier, and a high gain stage switchably coupled across the output of said operational amplifier.