Circuit arrangement for automatic zero level compensation

Claim 1

In a circuit for automatic balancing or compensating of an input signal to a drifting zero base line level including in series relationship a voltage-to-frequency converter to the input of which is applied the input signal being balanced, a counter for counting the output pulses of the voltage-to-frequency converter, and a digital-to-analog converter controlled by the counter, which generates an analog correction signal proportional to the counter reading, which correction signal is algebraically added to the input signal for base line level balancing, the improvement comprising: that the counter comprises two distinct groups of counter stages, one of said groups consisting of the more significant bit stages and the other of said groups consisting of the less significant bit stages; a fixed frequency pulse generator, the output of which is connected through a first controllable means to said one group of more significant bit counter stages; said first controllable means passing the output from said fixed frequency pulse generator to said one group of more significant bit counter stages only when said input signal differs from the desired zero base line level by more than a particular threshold value; The output of said voltage-to-frequency converter being connected through a second controllable means to said other group of less significant bit counter stages, said second controllable means passing the output of said voltage-to-frequency converter to said other group of less significant bit counter stages only when said input signal has been compensated relative to said desired zero base line level to within said particular threshold value, whereby coarse compensating of said input signal to said desired zero base level is obtained rapidly by the fixed frequency pulses causing the one group of more significant counter stages to store a value proportional to an approximate correction signal to within said threshold value, and then fine compensating of said input signal to said desired zero base line level is obtained from the voltage-to-frequency converter causing said other group of less significant counter stages to be driven at decreasing rate as the partially compensated input signal approaches closer and closer to the desired zero base level, so that rapid balancing of the input signal relative to the desired zero base line level is obtained, but without any overshooting of the desired compensation.