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US4968905A
Expired / Lapsed
US
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Temperature compensated high speed ECL-to-CMOS logic level translator
Assignee: BAE Systems PLC
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Filing: 1989-08-25
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Granted: 1990-11-06
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Expires: 2009-08-25
Abstract
Abstract An emitter coupled logic (ECL)-to-complementary metal-oxide-semiconductor (CMOS) logic level translator is temperature compensated to track temperature induced shifts in the ECL logic levels. The translator includes a differential amplifier with mid-range reference voltage. A reference voltage generator supplies the reference voltage to the differential amplifier and has a temperature sensitive transistor which changes the value of the circuit output (reference) voltage ambient with temperature shifts.
Inventors
- 👤 Ikuo J. Sanwo
- 👤 Gregory H. Milby
- 👤 Quynh-Giao X. Le
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 23:31
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/0175; H03K19/0185; H03K19/018507; H03K19/018521; H03K19/018528; H03K19/003; H03K19/00369; H03K19/00384; Y; Y10; Y10S; Y10S323/00; Y10S323/907
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
102 words
An emitter coupled logic (ECL)-to-complementary metal-oxide-semiconductor (CMOS) logic level translator comprising: a translator input coupled to receive an input ECL signal; a translator output; a logic level shifter coupled at its input to said translator input and coupled at its output to said translator output for translating said input ECL signal to an output CMOS signal; and temperature compensating means coupled to said logic level shifter for temperature compensating the output of said shifter; wherein said logic level shifter comprises a differential amplifier having a reference voltage input coupled to said temperature compensating means, said temperature compensating means supplying the reference voltage.
Claim 2
Dependent Claim
102 words
An emitter coupled logic (ECL)-to-complementary metal-oxide-semiconductor (CMOS) logic level translator comprising: a translator input coupled to receive an input ECL signal; a translator output; a logic level shifter coupled at its input to said translator input and coupled at its output to said translator output for translating said input ECL signal to an output CMOS signal; and temperature compensating means coupled to said logic level shifter for temperature compensating the output of said shifter; wherein said logic level shifter comprises a differential amplifier having a reference voltage input coupled to said temperature compensating means, said temperature compensating means supplying the reference voltage.
Claim 3
Dependent Claim
40 words
The logic level translator in claim 1 wherein said temperature compensating means comprises a temperature compensation transistor coupled to the output of said temperature compensating means for adjusting the output of said temperature compensating means in accordance with temperature changes.
Claim 4
Dependent Claim
33 words
The logic level translator in claim 1 further comprising a capacitor coupled between said logic level shifter and said temperature compensating means for stabilizing the reference voltage supplied to said logic level shifter.
Claim 5
Dependent Claim
67 words
The logic level translator in claim 1 further comprising a capacitor coupled between said logic level shifter and said temperature compensating means for stabilizing the reference voltage supplied to said logic level shifter, and wherein said temperature compensating means comprises a temperature compensation transistor coupled to the output of said temperature compensating means for adjusting the output of said temperature compensating means in accordance with temperature changes.
Claim 6
Dependent Claim
33 words
The logic level translator in claim 4 further comprising a capacitor coupled between said logic level shifter and said temperature compensating means for stabilizing the reference voltage supplied to said logic level shifter.
Claim 7
Dependent Claim
28 words
The logic level translator in claim 1 wherein said translator output comprises an inverter for outputting an inverted form of a signal received from said logic level shifter.
Claim 8
Dependent Claim
28 words
The logic level translator in claim 2 wherein said translator output comprises an inverter for outputting an inverted form of a signal received from said logic level shifter.
Claim 9
Dependent Claim
28 words
The logic level translator in claim 3 wherein said translator output comprises an inverter for outputting an inverted form of a signal received from said logic level shifter.
Claim 10
Dependent Claim
28 words
The logic level translator in claim 4 wherein said translator output comprises an inverter for outputting an inverted form of a signal received from said logic level shifter.
Claim 11
Dependent Claim
28 words
The logic level translator in claim 5 wherein said translator output comprises an inverter for outputting an inverted form of a signal received from said logic level shifter.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-11-05 | 1994-05-07 | 1994-11-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-11-05 | 1998-05-07 | 1998-11-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-11-05 | 2002-05-07 | 2002-11-06 | $7700.00 | Window Closed / Lapsed |