Patent US4968645A successfully refreshed from Google Patents.
US4968645A
Expired / Lapsed
US
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Method for manufacturing MOS/CMOS monolithic integrated circuits including silicide and polysilicon patterning
Assignee: STMicroelectronics SRL
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Filing: 1988-12-15
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Granted: 1990-11-06
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Expires: 2008-12-15
Abstract
Abstract A monolithic integrated circuit of either the MOS or CMOS type comprises an intermediate layer of polycrystalline silicon, a layer of a silicide of a refractory metal overlying said polycrystalline silicon layer, and regions of preset area and preset paths formed in the polycrystalline silicon layer and the silicide layer; the preset area regions and preset paths forming respectively high resistivity resistances and low resistivity interconnection lines for an intermediate connection level.
Inventors
- 👤 Livio Baldi
- 👤 Paolo G. Cappelletti
- 👤 Franco Maggioni
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 23:28
CPC Classifications
H; H10; H10D; H10D88/00; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/064; H10W20/066; H10W20/40; H10W20/41; H10W20/43; H10W20/44; H10W20/4451; Y; Y10; Y10S; Y10S148/00; Y10S148/019; Y10S148/106; Y10S148/136
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
109 words
A method of manufacturing a monolithic integrated circuit of either the MOS or CMOS type, comprising the following sequential steps of: providing a layer of polycrystalline silicon; depositing a layer of a silicide of a refractory metal over said layer of polycrystalline silicon; applying a mask onto said silicide layer to define regions of preset area; removing the silicide from said preset area regions to form resistance in an intermediate connection level; applying a mask onto said silicide layer and said regions to define preset paths adapted to form interconnection lines for said intermediate connection level; and removing the silicide layer and polycrystalline silicon layer from outside said mask.
Claim 2
Independent Claim
109 words
A method of manufacturing a monolithic integrated circuit of either the MOS or CMOS type, comprising the following sequential steps of: providing a layer of polycrystalline silicon; depositing a layer of a silicide of a refractory metal over said layer of polycrystalline silicon; applying a mask onto said silicide layer to define regions of preset area; removing the silicide from said preset area regions to form resistance in an intermediate connection level; applying a mask onto said silicide layer and said regions to define preset paths adapted to form interconnection lines for said intermediate connection level; and removing the silicide layer and polycrystalline silicon layer from outside said mask.
Claim 3
Independent Claim
110 words
A method of manufacturing a monolithic integrated circuit of either the MOS or CMOS type, comprising the following sequential steps of: providing a layer of polycrystalline silicon; depositing a layer of a silicide of a refractory metal over said layer of polycrystalline silicon; applying a mask onto said silicide layer to define regions of preset area and preset lines adapted to form interconnection lines for an intermediate connection level; removing the silicide layer and polycrystalline silicon layer from outside said mask; applying a mask onto said silicide layer to define said preset area regions; and removing the silicide from said preset area regions forming resistance in said intermediate connection level.
Claim 4
Independent Claim
110 words
A method of manufacturing a monolithic integrated circuit of either the MOS or CMOS type, comprising the following sequential steps of: providing a layer of polycrystalline silicon; depositing a layer of a silicide of a refractory metal over said layer of polycrystalline silicon; applying a mask onto said silicide layer to define regions of preset area and preset lines adapted to form interconnection lines for an intermediate connection level; removing the silicide layer and polycrystalline silicon layer from outside said mask; applying a mask onto said silicide layer to define said preset area regions; and removing the silicide from said preset area regions forming resistance in said intermediate connection level.
Claim 5
Independent Claim
23 words
A method according to any of claims 1 or 2, comprising an intermediate step of doping said polycrystalline silicon layer by ion implantation.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-11-05 | 1994-05-07 | 1994-11-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-11-05 | 1998-05-07 | 1998-11-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-11-05 | 2002-05-07 | 2002-11-06 | $7700.00 | Window Closed / Lapsed |