Dynamic RAM controller

Claim 1

DRAM controller apparatus for use with a DRAM array having a plurality of banks, each said bank having a coordinate address strobe input, said controller being responsive to a memory address signal for selecting one of said banks, said memory being operative in a memory access cycle wherein one of said banks is selected by selectively actuating said coordinate address strobe input thereof and a refresh cycle for refreshing said DRAM array in response to a refresh request signal by simultaneously actuating said coordinate address strobe inputs of all said banks, comprising first circuit means including encoding means responsive to said memory address signal for providing an encoded digital coordinate address strobe signal representative of said selected bank and having a number of bits smaller than the number of said banks, second circuit means including decoding means and polarity inverting means, and bus means for coupling said encoded digital coordinate address strobe signal from said first circuit means to said second circuit means, said decoding means comprising means having a plurality of outputs coupled respectively to said coordinate address strobe inputs of said banks and responsive to said encoded digital coordinate address strobe signal for selectively energizing one of said outputs in accordance therewith, thereby selecting said bank corresponding to said encoded digital coordinate address strobe signal, said polarity inverting means comprising means responsive to said refresh request signal for simultaneously inverting the polarity of all of said outputs, thereby effecting said refresh cycle.