US4887240A
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US
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Staggered refresh for dram array
Assignee: National Semiconductor Corp
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Filing: 1987-12-15
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Granted: 1989-12-12
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Expires: 2007-12-15
Abstract
Abstract According to the present invention, each successive refresh to the multiple banks of a DRAM array is staggered by one clock period. Thus, the time required to refresh one row in each DRAM of each bank at 10 MHz, for example, is equal to 0.7 μsec., or 4.4% of the total allowable maximum time between refresh cycles. This staggered refresh technique avoids large power supply current spikes while minimizing the effect on memory access bandwidth.
Inventors
- 👤 Timothy L. Garverick
- 👤 Farid A. Yazdy
- 👤 Richard D. Henderson
- 👤 Webster B. Meier
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 21:38
CPC Classifications
G; G11; G11C; G11C7/00; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/406
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
178 words
A refresh circuit for generating a plurality of refresh signals for a dynamic random access memory (DRAM) comprising memory cells subdivided into a plurality of memory cell banks such that the refresh signals are provided to the memory cell banks in one-to-one correspondence to refresh the memory cells comprising the respective memory cell bank, the refresh circuit comprising a plurality of edge-triggered flip-flops connected in series such that the data input signal to successive flip-flops in the series is provided by an output of the previous flip-flop in the series such that successive flip-flops generate a sequence of refresh signals in response to successive cycles of a clock signal commonly connected to each of the flip-flops, the refresh signals being connected to one-to-one correspondence to the memory cell banks and wherein an output of the last flip-flop in the series of flip-flops is provided via an inverter as the data input signal to the first flip-flop in the series to provide sequential termination of the refresh signals on a subsequent sequence of successive cycles of the clock signal.
Claim 2
Dependent Claim
178 words
A refresh circuit for generating a plurality of refresh signals for a dynamic random access memory (DRAM) comprising memory cells subdivided into a plurality of memory cell banks such that the refresh signals are provided to the memory cell banks in one-to-one correspondence to refresh the memory cells comprising the respective memory cell bank, the refresh circuit comprising a plurality of edge-triggered flip-flops connected in series such that the data input signal to successive flip-flops in the series is provided by an output of the previous flip-flop in the series such that successive flip-flops generate a sequence of refresh signals in response to successive cycles of a clock signal commonly connected to each of the flip-flops, the refresh signals being connected to one-to-one correspondence to the memory cell banks and wherein an output of the last flip-flop in the series of flip-flops is provided via an inverter as the data input signal to the first flip-flop in the series to provide sequential termination of the refresh signals on a subsequent sequence of successive cycles of the clock signal.
Claim 3
Dependent Claim
178 words
Refresh circuitry for providing refresh signals to the memory cells of a dynamic random access memory (DRAM) wherein an individual memory cell is accessed by application of a corresponding address signal to address inputs of the DRAM in correspondence to cycles of a system clock signal applied to the DRAM, and wherein the memory cells are subdivided into a plurality of memory cell banks and a single refresh signal is periodically provided to each memory cell bank to refresh the memory cells comprising that memory cell bank, the refresh circuitry comprising: (a) means responsive to the system clock signal for generating a sequence of individual refresh signals, successive individual refresh signals in the sequence being initiated on successive cycles of the system clock signal; and (b) means for sequentially providing each individual refresh signal to a corresponding memory cell bank on successive cycles of the system clock signal and in one-to-one correspondence to the memory cell banks such that refresh of the plurality of memory cell banks is sequentially initiated on successive cycles of the system clock signal.
Claim 4
Dependent Claim
178 words
Refresh circuitry for providing refresh signals to the memory cells of a dynamic random access memory (DRAM) wherein an individual memory cell is accessed by application of a corresponding address signal to address inputs of the DRAM in correspondence to cycles of a system clock signal applied to the DRAM, and wherein the memory cells are subdivided into a plurality of memory cell banks and a single refresh signal is periodically provided to each memory cell bank to refresh the memory cells comprising that memory cell bank, the refresh circuitry comprising: (a) means responsive to the system clock signal for generating a sequence of individual refresh signals, successive individual refresh signals in the sequence being initiated on successive cycles of the system clock signal; and (b) means for sequentially providing each individual refresh signal to a corresponding memory cell bank on successive cycles of the system clock signal and in one-to-one correspondence to the memory cell banks such that refresh of the plurality of memory cell banks is sequentially initiated on successive cycles of the system clock signal.
Claim 5
Dependent Claim
47 words
Refresh circuitry as in claim 2 and wherein the means for providing each individual refresh signal to its corresponding memory cell bank includes means for applying each individual refresh signal to its corresponding memory cell bank for a preselected number of cycles of the system clock signal.
Claim 6
Dependent Claim
36 words
Refresh circuitry as in claim 3 and further comprising means for terminating application of each individual refresh signal to its corresponding memory cell bank on a subsequent sequence of successive cycles of the system clock signal.
Claim 7
Independent Claim
173 words
A method of refreshing the memory cells of a dynamic random access memory (DRAM) wherein an individual memory cell is accessed by application of a corresponding address signal to address inputs of the DRAM in correspondence to cycles of a system clock signal applied to the DRAM, and wherein the memory cells are subdivided into a plurality of memory cell banks and an individual of the refresh signals is periodically provided to a corresponding memory cell bank to refresh the memory cells comprising that memory cell bank, the method comprising: (a) generating a sequence of individual refresh signals in response to the system clock signal, successive individual refresh signals in the sequence being initiated on successive cycles of the system clock signal; (b) providing individual of the refresh signals to its corresponding memory cell bank on successive cycles of the system clock signal and in one-to-one correspondence to the memory cell banks such that refresh of the plurality of memory cell banks is sequentially initiated on successive cycles of the system clock signal.
Claim 8
Independent Claim
173 words
A method of refreshing the memory cells of a dynamic random access memory (DRAM) wherein an individual memory cell is accessed by application of a corresponding address signal to address inputs of the DRAM in correspondence to cycles of a system clock signal applied to the DRAM, and wherein the memory cells are subdivided into a plurality of memory cell banks and an individual of the refresh signals is periodically provided to a corresponding memory cell bank to refresh the memory cells comprising that memory cell bank, the method comprising: (a) generating a sequence of individual refresh signals in response to the system clock signal, successive individual refresh signals in the sequence being initiated on successive cycles of the system clock signal; (b) providing individual of the refresh signals to its corresponding memory cell bank on successive cycles of the system clock signal and in one-to-one correspondence to the memory cell banks such that refresh of the plurality of memory cell banks is sequentially initiated on successive cycles of the system clock signal.
Claim 9
Dependent Claim
33 words
A method as in claim 5 and including the step of applying each individual refresh signal to its corresponding memory cell bank for a preselected number of cycles of the system clock signal.
Claim 10
Dependent Claim
36 words
A method as in claim 6 and including the step of terminating application of each individual refresh signal to its corresponding memory cell bank on a subsequent sequence of successive cycles of the system clock signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-12-11 | 1993-06-12 | 1993-12-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-12-11 | 1997-06-12 | 1997-12-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-12-11 | 2001-06-12 | 2001-12-12 | $7700.00 | Window Closed / Lapsed |