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US4962052A
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Method for producing semiconductor integrated circuit device
Assignee: Hitachi Ltd
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Filing: 1990-02-07
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Granted: 1990-10-09
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Expires: 2010-02-07
Abstract
Abstract A method for producing a memory LSI having in its peripheral circuitry an MISFET of LDD structure and a vertical type bipolar transistor is disclosed. More particularly, an impurity for forming a low impurity concentration region of the said MISFET of LDD structure is introduced sideways of an emitter-base junction of the bipolar transistor. By the introduction of the said impurity, an effective impurity concentration near the base surface is reduced and the cut-off frequency of the bipolar transistor is improved.
Inventors
- 👤 Kyoichiro Asayama
- 👤 Hiroyuki Miyazawa
- 👤 Yutaka Kobayashi
- 👤 Seigou Yukutake
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 21:09
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/10; H10D; H10D10/00; H10D10/01; H10D10/051; H10D62/00; H10D62/10; H10D62/17; H10D62/177; H10D84/00; H10D84/01; H10D84/0107; H10D84/0109; H10D84/02; H10D84/03; H10D84/038; H10D84/40; H10D84/401; H10D84/80
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
275 words
A method for manufacturing a semiconductor device including at least one MOSFET and at least one bipolar transistor, comprising the steps of: (a) providing a semiconductor body having a main surface, said body including a first semiconductor region of a first conductivity type in which a MOSFET is to be formed, and a second semiconductor region of a second conductivity type opposite to said first conductivity type, in which a bipolar transistor is to be formed, in said main surface; (b) forming a gate electrode of said MOSFET on said first semiconductor region through a gate insulating film; (c) introducing a first impurity of said second conductivity type into a surface of said first semiconductor region at both sides of said gate electrode, and also introducing simultaneously said first impurity into a surface of said second semiconductor region, whereby there are formed a pair of third semiconductor regions serving as part of source and drain regions of said MOSFET in said first semiconductor region and a fourth semiconductor region in said second semiconductor region; (d) introducing a second impurity of a higher concentration that than of said fourth semiconductor region, of said first conductivity type, into said second semiconductor region, whereby there is formed a fifth semiconductor region of said first conductivity type serving as a base region of said fourth semiconductor region, so as to overlap with said fourth semiconductor region; and (e) introducing a third impurity of said second conductivity type having a concentration higher than that of said first impurity into said fifth semiconductor region, whereby there is formed a sixth semiconductor region serving as an emitter region of said bipolar transistor.
Claim 2
Independent Claim
275 words
A method for manufacturing a semiconductor device including at least one MOSFET and at least one bipolar transistor, comprising the steps of: (a) providing a semiconductor body having a main surface, said body including a first semiconductor region of a first conductivity type in which a MOSFET is to be formed, and a second semiconductor region of a second conductivity type opposite to said first conductivity type, in which a bipolar transistor is to be formed, in said main surface; (b) forming a gate electrode of said MOSFET on said first semiconductor region through a gate insulating film; (c) introducing a first impurity of said second conductivity type into a surface of said first semiconductor region at both sides of said gate electrode, and also introducing simultaneously said first impurity into a surface of said second semiconductor region, whereby there are formed a pair of third semiconductor regions serving as part of source and drain regions of said MOSFET in said first semiconductor region and a fourth semiconductor region in said second semiconductor region; (d) introducing a second impurity of a higher concentration that than of said fourth semiconductor region, of said first conductivity type, into said second semiconductor region, whereby there is formed a fifth semiconductor region of said first conductivity type serving as a base region of said fourth semiconductor region, so as to overlap with said fourth semiconductor region; and (e) introducing a third impurity of said second conductivity type having a concentration higher than that of said first impurity into said fifth semiconductor region, whereby there is formed a sixth semiconductor region serving as an emitter region of said bipolar transistor.
Claim 3
Dependent Claim
34 words
A method according to claim 1, wherein by the introduction of said second impurity, said fourth semiconductor region changes into a semiconductor region of said first conductivity type and becomes a seventh semiconductor region.
Claim 4
Dependent Claim
29 words
A method according to claim 2, wherein an impurity concentration of said seventh semiconductor region, of said first conductivity type, is lower than that of said fifth semiconductor region.
Claim 5
Dependent Claim
22 words
A method according to claim 3, wherein said seventh and fifth semiconductor regions integrally form said base region of said bipolar transistor.
Claim 6
Dependent Claim
23 words
A method according to claim 4, wherein the depth of said sixth semiconductor region is larger than that of said seventh semiconductor region.
Claim 7
Dependent Claim
22 words
A method according to claim 1, wherein said first conductivity type is P type, while said second conductivity type is N type.
Claim 8
Dependent Claim
26 words
A method according to claim 1, wherein said semiconductor body is an ipitaxial layer formed on a main surface of a first conductivity type semiconductor substrate.
Claim 9
Dependent Claim
26 words
A method according to claim 7, wherein said first semiconductor region is a well region and is electrically connected with said first conductivity type semiconductor substrate.
Claim 10
Dependent Claim
20 words
A method according to claim 7, wherein said second semiconductor region serves as a collector region of said bipolar transistor.
Claim 11
Dependent Claim
25 words
A method according to claim 9, wherein a diffusion layer for drawing-out a collector of said bipolar transistor is formed in said second semiconductor region.
Claim 12
Dependent Claim
65 words
A method according to claim 1, further comprising a step of introducing a fourth impurity of said second conductivity type, having a concentration higher than that of said first impurity, into said first semiconductor region at both sides of said gate electrode, whereby there is formed a pair of eighth semiconductor regions serving as a part of said source and drain regions of said MOSFET.
Claim 13
Dependent Claim
30 words
A method according to claim 11, wherein said pair of third semiconductor regions and said pair of eighth semiconductor regions integrally form the source and drain regions of said MOSFET.
Claim 14
Dependent Claim
14 words
A method according to claim 12, wherein said MOSFET is of an LDD structure.
Claim 15
Dependent Claim
20 words
A method according to claim 11, wherein said fourth and third impurities of said second conductivity type are simultaneously introduced.
Claim 16
Dependent Claim
38 words
A method according to claim 1, wherein said semiconductor body has a ninth semiconductor region of said second conductivity type in said main surface, and wherein a first conductivity type MOSFET is formed in said ninth semiconductor region.
Claim 17
Dependent Claim
51 words
A method according to claim 15, wherein said semiconductor body further has a tenth semiconductor region of said first conductivity type, and wherein a second conductivity type MOSFET and capacitor electrically connected in series with a source region of said second conductivity type MOSFET are formed in said tenth semiconductor region.
Claim 18
Dependent Claim
20 words
A method according to claim 16, wherein said tenth semiconductor region is a memory cell forming region of a DRAM.
References Cited (Backward Citations)
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