Apparatus, method and data structure for validation of kernel data bus

Claim 1

A method for validation of the data bus of a micro-processor based unit under test (UUT) comprising the steps of (a.) performing a load operation of a first bit pattern containing a number of bits equal to one-half the number of lines in at least a portion of said data bus over a first plurality of lines in said data bus, (b.) performing a load operation of a second bit pattern which is the complement of said first bit pattern over a second plurality of bus lines of said data bus lines, (c.) comparing said first and second bit patterns to determine whether said second bit pattern is the complement of said second bit pattern to determine if said second bit pattern is not the complement of said first bit pattern, (d.) performing a load operation of a third bit pattern containing a number of bits equal to one-half the number of lines in at least a portion of said data bus over a third plurality of lines in said data bus, (e.) performing a load operation of a fourth bit pattern which is not the complement of said third bit pattern over a fourth plurality of bus lines of said data bus lines, (f.) comparing said third and fourth bit patterns to determine if said fourth bit pattern is not the complement of said third bit pattern, and (g.) validating said data bus based upon the results of steps (c.) and (f.).

Claim 2

A method for validation of the data bus of a micro-processor based unit under test (UUT) comprising the steps of (a.) performing a load operation of a first bit pattern containing a number of bits equal to one-half the number of lines in at least a portion of said data bus over a first plurality of lines in said data bus, (b.) performing a load operation of a second bit pattern which is the complement of said first bit pattern over a second plurality of bus lines of said data bus lines, (c.) comparing said first and second bit patterns to determine whether said second bit pattern is the complement of said second bit pattern to determine if said second bit pattern is not the complement of said first bit pattern, (d.) performing a load operation of a third bit pattern containing a number of bits equal to one-half the number of lines in at least a portion of said data bus over a third plurality of lines in said data bus, (e.) performing a load operation of a fourth bit pattern which is not the complement of said third bit pattern over a fourth plurality of bus lines of said data bus lines, (f.) comparing said third and fourth bit patterns to determine if said fourth bit pattern is not the complement of said third bit pattern, and (g.) validating said data bus based upon the results of steps (c.) and (f.).

Claim 7

An apparatus for validation of the data bus of a micro-processor based unit under test (UUT) comprising: first means for forcing onto said data bus a first bit pattern containing a number of bits equal to one-half the number of lines in at least a portion of said data bus over a first plurality of lines in said data bus and forcing onto said data bus a second bit pattern which is the complement of said first bit pattern over a second plurality of bus lines of said data bus lines, second means for forcing onto said data bus a third bit pattern containing a number of bits equal to one-half the number of lines in at least a portion of said data bus over a third plurality of lines in said data bus and forcing of a fourth bit pattern which is not the complement of said third bit pattern over a fourth plurality of bus lines of said data bus lines, means for comparing said first and second bit patterns and comparing said third and fourth bit patterns and generating a signal if said second bit pattern is not the complement of said first bit pattern and if said fourth bit pattern is not the complement of said third bit pattern, and means for evaluating the signals produced by said means for comparing to validate said data bus.

Claim 8

An apparatus for validation of the data bus of a micro-processor based unit under test (UUT) comprising: first means for forcing onto said data bus a first bit pattern containing a number of bits equal to one-half the number of lines in at least a portion of said data bus over a first plurality of lines in said data bus and forcing onto said data bus a second bit pattern which is the complement of said first bit pattern over a second plurality of bus lines of said data bus lines, second means for forcing onto said data bus a third bit pattern containing a number of bits equal to one-half the number of lines in at least a portion of said data bus over a third plurality of lines in said data bus and forcing of a fourth bit pattern which is not the complement of said third bit pattern over a fourth plurality of bus lines of said data bus lines, means for comparing said first and second bit patterns and comparing said third and fourth bit patterns and generating a signal if said second bit pattern is not the complement of said first bit pattern and if said fourth bit pattern is not the complement of said third bit pattern, and means for evaluating the signals produced by said means for comparing to validate said data bus.