Low di/dt output buffer with improved speed

Claim 2

In an integrated circuit, an output buffer for providing an output signal to said integrated circuit, comprising: voltage regulator means, coupled to a first power supply voltage terminal and a second power supply voltage terminal, for providing a regulated voltage signal characterized as having a constant voltage substantially independent of fluctuations between the first power supply voltage terminal and the second power supply voltage terminal; a predriver, said predriver having a positive power supply input terminal and a negative power supply input terminal, wherein said positive power supply terminal is coupled to the regulated voltage signal, and said negative power supply terminal is coupled to the second power supply voltage terminal, said predriver providing a regulated predriven signal in response to an input signal; and an output stage coupled to said first power supply voltage terminal and to said second power supply voltage terminal, said output stage receiving the regulated predriven signal and providing said output signal in response thereto.

Claim 3

The output buffer of claim 1, wherein said output signal is coupled to a bonding pad, said bonding pad providing a point for connection external to the integrated circuit.

Claim 4

An output buffer for a high speed integrated circuit, said output buffer receiving a first input signal and a second input signal and providing an output signal external to said high speed integrated circuit, comprising: first voltage regulator means, coupled to a first power supply voltage terminal and a second power supply voltage terminal, for providing a first regulated voltage signal characterized as having a constant voltage substantially independent of fluctuations between the first power supply voltage terminal and the second power supply voltage terminal; second voltage regulator means, coupled to the first power supply voltage terminal and the second power supply voltage terminal, for providing a second regulated voltage signal characterized as having a constant voltage substantially independent of fluctuations between the first power supply voltage terminal and the second power supply voltage terminal; a first predriver, said first predriver having a positive power supply input terminal and a negative power supply input terminal, wherein said positive power supply terminal is coupled to a first regulated voltage signal, and said negative power supply terminal is coupled to the second power supply voltage terminal, said first predriver providing a first regulated predriven signal in response to a first input signal; a second predriver, said second predriver having a positive power supply input terminal and a negative power supply input terminal, wherein said positive power supply terminal is coupled to a second regulated voltage signal, and said negative power supply terminal is coupled to the second power supply voltage terminal, said second predriver providing a second regulated predriven signal in response to a second input signal; and an output stage, said output stage receiving the first regulated predriven signal and the second regulated predriven signal and providing said output signal in response thereto.

Claim 5

An output buffer for a high speed integrated circuit, said output buffer receiving a first input signal and a second input signal and providing an output signal external to said high speed integrated circuit, comprising: first voltage regulator means, coupled to a first power supply voltage terminal and a second power supply voltage terminal, for providing a first regulated voltage signal characterized as having a constant voltage substantially independent of fluctuations between the first power supply voltage terminal and the second power supply voltage terminal; second voltage regulator means, coupled to the first power supply voltage terminal and the second power supply voltage terminal, for providing a second regulated voltage signal characterized as having a constant voltage substantially independent of fluctuations between the first power supply voltage terminal and the second power supply voltage terminal; a first predriver, said first predriver having a positive power supply input terminal and a negative power supply input terminal, wherein said positive power supply terminal is coupled to a first regulated voltage signal, and said negative power supply terminal is coupled to the second power supply voltage terminal, said first predriver providing a first regulated predriven signal in response to a first input signal; a second predriver, said second predriver having a positive power supply input terminal and a negative power supply input terminal, wherein said positive power supply terminal is coupled to a second regulated voltage signal, and said negative power supply terminal is coupled to the second power supply voltage terminal, said second predriver providing a second regulated predriven signal in response to a second input signal; and an output stage, said output stage receiving the first regulated predriven signal and the second regulated predriven signal and providing said output signal in response thereto.

Claim 6

The output buffer of claim 3, wherein said first predriver comprises: a first transistor having a first current electrode for receiving the first regulated voltage signal, a control electrode for receiving the first input signal, and a second current electrode for providing a first regulated predriven signal; a second transistor having a first current electrode connected to the second current electrode of the first transistor, a control electrode for receiving the first input signal, and a second current electrode; and a first resistor having a first terminal connected to the second current electrode of the second transistor and a second terminal coupled to the second power supply voltage terminal.

Claim 7

The output buffer of claim 3, wherein said second predriver comprises: a third transistor having a first current electrode for receiving the second regulated voltage signal, a control electrode for receiving the second input signal, and a second current electrode for providing a second regulated predriven signal; a fourth transistor having a first current electrode connected to the second current electrode of the third transistor, a control electrode for receiving the second input signal, and a second current electrode; and a second resistor having a first terminal connected to the second current electrode of the fifth transistor and a second terminal coupled to the second power supply voltage terminal.

Claim 8

The output buffer of claim 3 wherein said output stage comprises: a fifth transistor having a first current electrode coupled to the first power supply voltage terminal, a control electrode for receiving the first regulated predriven signal, and a second current electrode for supplying an output signal; a sixth transistor having a first current electrode connected to the second terminal of the fifth transistor, a control electrode for receiving the second regulated predriven signal, and a second current electrode coupled to the second power supply voltage terminal.

Claim 9

An output buffer for a high speed integrated circuit, said output buffer receiving a first input signal and a second input signal and providing an output signal external to said high speed integrated circuit, comprising: voltage regulator means, coupled to a first power supply voltage terminal and a second power supply voltage terminal, for providing a regulated voltage signal characterized as having a constant voltage substantially independent of fluctuations between the first power supply voltage terminal and the second power supply voltage terminal; a first transistor having a first current electrode for receiving the regulated voltage signal, a control electrode for receiving the first input signal, and a second current electrode for providing a first regulated predriven signal; a second transistor having a first current electrode connected to the second current electrode of the first transistor, a control electrode for receiving the first input signal, and a second current electrode; a first resistor having a first terminal connected to the second current electrode of the second transistor and a second terminal coupled to the second power supply voltage terminal; a third transistor having a first current electrode coupled to the first power supply voltage terminal, a control electrode for receiving the first regulated predriven signal, and a second current electrode for supplying an output signal; a fourth transistor having a first current electrode for receiving the regulated voltage signal, a control electrode for receiving the second input signal, and a second current electrode for providing a second regulated predriven signal; a fifth transistor having a first current electrode connected to the second current electrode of the fourth transistor, a control electrode for receiving the second input signal, and a second current electrode; a second resistor having a first terminal connected to the second current electrode of the fifth transistor and a second terminal coupled to the second power supply voltage terminal; a sixth transistor having a first current electrode connected to the second terminal of the third transistor, a control electrode for receiving the second regulated predriven signal, and a second current electrode coupled to the second power supply voltage terminal.

Claim 10

An output buffer for a high speed integrated circuit, said output buffer receiving a first input signal and a second input signal and providing an output signal external to said high speed integrated circuit, comprising: voltage regulator means, coupled to a first power supply voltage terminal and a second power supply voltage terminal, for providing a regulated voltage signal characterized as having a constant voltage substantially independent of fluctuations between the first power supply voltage terminal and the second power supply voltage terminal; a first transistor having a first current electrode for receiving the regulated voltage signal, a control electrode for receiving the first input signal, and a second current electrode for providing a first regulated predriven signal; a second transistor having a first current electrode connected to the second current electrode of the first transistor, a control electrode for receiving the first input signal, and a second current electrode; a first resistor having a first terminal connected to the second current electrode of the second transistor and a second terminal coupled to the second power supply voltage terminal; a third transistor having a first current electrode coupled to the first power supply voltage terminal, a control electrode for receiving the first regulated predriven signal, and a second current electrode for supplying an output signal; a fourth transistor having a first current electrode for receiving the regulated voltage signal, a control electrode for receiving the second input signal, and a second current electrode for providing a second regulated predriven signal; a fifth transistor having a first current electrode connected to the second current electrode of the fourth transistor, a control electrode for receiving the second input signal, and a second current electrode; a second resistor having a first terminal connected to the second current electrode of the fifth transistor and a second terminal coupled to the second power supply voltage terminal; a sixth transistor having a first current electrode connected to the second terminal of the third transistor, a control electrode for receiving the second regulated predriven signal, and a second current electrode coupled to the second power supply voltage terminal.

Claim 11

The output buffer of claim 7, wherein said output signal is coupled to a bonding pad, said bonding pad providing a point for connection external to the high speed integrated circuit.

Claim 12

In an integrated circuit comprising a chip and a package and interconnections therebetween, wherein said chip comprises functional circuitry, wherein a bonding pad provides an interconnection point between the functional circuitry and the package, an output buffer in the functional circuitry, comprising: voltage regulator means, coupled to a first power supply voltage terminal and a second power supply voltage terminal, for providing a regulated voltage signal characterized as having a constant voltage substantially independent of fluctuations between the first power supply voltage terminal and the second power supply voltage terminal; predriver means for receiving the regulated voltage signal and a data input signal, and providing a regulated predriven signal in response to the data input signal; and an output stage coupled to said first power supply voltage terminal and to said second power supply voltage terminal, said output stage receiving the regulated predriven signal and providing an output signal on the bonding pad in response thereto.

Claim 13

In an integrated circuit comprising a chip and a package and interconnections therebetween, wherein said chip comprises functional circuitry, wherein a bonding pad provides an interconnection point between the functional circuitry and the package, an output buffer in the functional circuitry, comprising: voltage regulator means, coupled to a first power supply voltage terminal and a second power supply voltage terminal, for providing a regulated voltage signal characterized as having a constant voltage substantially independent of fluctuations between the first power supply voltage terminal and the second power supply voltage terminal; predriver means for receiving the regulated voltage signal and a data input signal, and providing a regulated predriven signal in response to the data input signal; and an output stage coupled to said first power supply voltage terminal and to said second power supply voltage terminal, said output stage receiving the regulated predriven signal and providing an output signal on the bonding pad in response thereto.

Claim 14

The output buffer of claim 9, wherein said predriver means comprises: a first transistor having a first current electrode for receiving the regulated voltage signal, a control electrode for receiving the data input signal, and a second current electrode for providing a first regulated predriven signal; a second transistor having a first current electrode connected to the second current electrode of the first transistor, a control electrode for receiving the data input signal, and a second current electrode; and a first resistor having a first terminal connected to the second current electrode of the second transistor and a second terminal coupled to the second power supply voltage terminal.

Claim 15

The output buffer of claim 9 wherein said output stage comprises a third transistor having a first current electrode coupled to said bonding pad, a control electrode coupled to the second current electrode of the first transistor, and a second current electrode coupled to the second power supply voltage terminal.