US4953164A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Cache memory system having error correcting circuit
Assignee: Mitsubishi Electric Corp
•
Filing: 1988-10-06
•
Granted: 1990-08-28
•
Expires: 2008-10-06
Abstract
Abstract There are provided a first memory cell array and a second memory cell array. The first memory cell array comprises a dynamic RAM and the second memory cell array comprises a static RAM. In addition, the second memory cell array has smaller capacity than that of the first memory cell array. An error correcting circuit, a check bit generating circuit and a register are connected between the first memory cell array and the second memory cell array. Data which is frequently accessed is transferred from the first memory cell array to the second memory cell array and stored therein. Access is made to the second memory cell array. When data which is required is not in the second memory cell array, access is made to the first memory cell array. At the time of transferring data from the first memory cell array to the second memory cell array, errors are corrected by the error correcting circuit. The check bit generating circuit is responsive to data whose error is corrected by the error correcting circuit for generating new check bits.
Inventors
- 👤 Mikio Asakura
- 👤 Kazuyasu Fujishima
- 👤 Yoshio Matsuda
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 13:06
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/10; G06F11/1008; G06F11/1064; G06F12/00; G06F12/02; G06F12/08; G06F12/0802
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
237 words
A semiconductor memory device for storing information bits including a plurality of bits and check bits for detecting and correcting an error in both the information bits and the check bits or an error in the information bits, comprising, on a single chip; check bit generating means responsive to said information bits for generating said check bits, first storing means for storing a plurality of sets of said information bits and said check bits generated by said check bit generating means, error correcting means for detecting and correcting the error in both said information bits and said check bits or the error in said information bits using said check bits corresponding to said information bits, first transferring means for transferring to said error correcting means said information bits and said check bits corresponding thereto, stored in said first storing means, second storing means to which access can be made faster than the access speed to said first storing means and for storing some of said information bits, said second storing means comprising a cache memory means for accessing data stored therein during a reading operation whenever data stored therein corresponds to an externally applied address signal, the capacity of said second storing means being less than the capacity of said first storing means, and second transferring means for transferring to said second storing means said information bits already corrected for any error by said error correcting means.
Claim 2
Dependent Claim
237 words
A semiconductor memory device for storing information bits including a plurality of bits and check bits for detecting and correcting an error in both the information bits and the check bits or an error in the information bits, comprising, on a single chip; check bit generating means responsive to said information bits for generating said check bits, first storing means for storing a plurality of sets of said information bits and said check bits generated by said check bit generating means, error correcting means for detecting and correcting the error in both said information bits and said check bits or the error in said information bits using said check bits corresponding to said information bits, first transferring means for transferring to said error correcting means said information bits and said check bits corresponding thereto, stored in said first storing means, second storing means to which access can be made faster than the access speed to said first storing means and for storing some of said information bits, said second storing means comprising a cache memory means for accessing data stored therein during a reading operation whenever data stored therein corresponds to an externally applied address signal, the capacity of said second storing means being less than the capacity of said first storing means, and second transferring means for transferring to said second storing means said information bits already corrected for any error by said error correcting means.
Claim 3
Dependent Claim
63 words
A semiconductor memory device according to claim 1, wherein said first storing means further comprises refreshing means for refreshing each of said memory cells, and said error correcting means detects and corrects the error in both the information bits and check bits or the error in the information bits at the time of refreshing each of the memory cells by said refreshing means.
Claim 4
Dependent Claim
223 words
A semiconductor memory device according to claim 1, wherein said first storing means comprises a plurality of memory cells arranged in a plurality of rows and columns and is divided into a plurality of blocks, each of said blocks comprising memory cells arranged in a plurality of columns, each of said information bits and each of said check bits corresponding thereto being stored in any row in any of said blocks, said second storing means comprises a plurality of memory cells arranged in a plurality of rows and columns and is divided into a plurality of blocks, each of said blocks comprising memory cells arranged in a plurality of columns, each of said information bits being stored in any row in any of said blocks, the number of the memory cells in said second storing means is smaller than the number of memory cells which store said information bits, of the memory cells in said first storing means, said first transferring means comprises first row selecting means for selecting one row in said first storing means and first block selecting means for selecting one block of said first storing means, and said second transferring means comprises second row selecting means for selecting one row in said second storing means and second block selecting means for selecting one block of said second storing means.
Claim 5
Dependent Claim
40 words
A semiconductor memory device according to claim 3, wherein the memory cell included in said first storing means each comprise a dynamic memory cell and the memory cells included in said second storing means each comprise a static memory cell.
Claim 6
Dependent Claim
46 words
A semiconductor memory device according to claim 1, which further comprises bit selecting means for selecting the bit to which access is required from among said information bits, and column selecting means for selecting the column to which access is required in said second storing means.
Claim 7
Dependent Claim
40 words
A semiconductor memory device according to claim 5, wherein the memory cells included in said first storing means each comprise a dynamic memory cell, and the memory cells included in said second storing means each comprise a static memory cell.
Claim 8
Dependent Claim
46 words
A semiconductor memory device according to claim 3, which further comprises bit selecting means for selecting the bit to which access is required from among said information bits, and column selecting means for selecting the column to which access is required in said second storing means.
Claim 9
Dependent Claim
62 words
A semiconductor memory device according to claim 7, which further comprises a first input/output terminal for inputting or outputting one bit information to or from said bit selecting means, and a second input/output terminal for inputting or outputting information to or from a memory cell in said second storing means selecting by said second row selecting means and said column selecting means.
Claim 10
Dependent Claim
62 words
A semiconductor memory device according to claim 5, which further comprises a first input/output terminal for inputting or outputting one bit information to or from said bit selecting means, and a second input/output terminal for inputting or outputting information to or from a memory cell in said second storing means selected by said second row selecting means and said column selecting means.
Claim 11
Dependent Claim
40 words
A semiconductor memory device according to claim 9, wherein the memory cells included in said first storing means each comprise a dynamic memory cell, and the memory cells included in said second storing means each comprise a static memory cell.
Claim 12
Dependent Claim
282 words
A semiconductor memory device for storing information bits including a plurality of bits and checks for detecting and correcting an error in both the information bits and the check bits or an error in the information bits, comprising, on a single chip: check bit generating means responsive to said information bits for generating said check bits, first storing means for storing a plurality of sets of said information bits and said check bits generated by said check bit generating means, error correcting means for detecting and correcting the error in both said information bits and said check bits or the error in said information bits using said check bits corresponding to said information bits, first transferring means for transferring to said error correcting means said information bits and said check bits corresponding thereto, stored in said first storing means, second storing means to which access can be made faster than the across speed to said first storing means and for storing some of said information bits, said second storing means comprising a cache memory means for accessing data stored therein during a reading operation whenever data stored therein corresponds to an externally applied address signal, the capacity of said second storing means being less than the capacity of said first storing means, and second transferring means for transferring to said second storing means said information bits, wherein said error correcting means detects but does not correct an error when said information bits and said check bits stored in said first storing means are transferred to said error correcting means by said first transferring means and the informatin bits are further transferred, uncorrected, to said second storing means by said second transferring means.
Claim 13
Dependent Claim
282 words
A semiconductor memory device for storing information bits including a plurality of bits and checks for detecting and correcting an error in both the information bits and the check bits or an error in the information bits, comprising, on a single chip: check bit generating means responsive to said information bits for generating said check bits, first storing means for storing a plurality of sets of said information bits and said check bits generated by said check bit generating means, error correcting means for detecting and correcting the error in both said information bits and said check bits or the error in said information bits using said check bits corresponding to said information bits, first transferring means for transferring to said error correcting means said information bits and said check bits corresponding thereto, stored in said first storing means, second storing means to which access can be made faster than the across speed to said first storing means and for storing some of said information bits, said second storing means comprising a cache memory means for accessing data stored therein during a reading operation whenever data stored therein corresponds to an externally applied address signal, the capacity of said second storing means being less than the capacity of said first storing means, and second transferring means for transferring to said second storing means said information bits, wherein said error correcting means detects but does not correct an error when said information bits and said check bits stored in said first storing means are transferred to said error correcting means by said first transferring means and the informatin bits are further transferred, uncorrected, to said second storing means by said second transferring means.
Claim 14
Independent Claim
306 words
A method for controlling a semiconductor memory device for storing information bits including, on a single chip, a plurality of bits and check bits used for detecting and correcting an error in both the information bits and the check bits or an error in the information bits, comprising check bit generating means responsive to said information bits for generating said check bits; first storing means for storing a plurality of sets of said information bits and said check bits generated by said check bit generating means; error correcting means for detecting and correcting the error in both said information bits and said check bits or the error in said information bits using said check bits corresponding to said information bits; and second storing means comprising a cache memory having smaller memory capacity than said first storing means, and to which access can be made faster than the access speed to said first storing means, and for storing some of said information bits, comprising: a first read operation, a second read operation, a first write operation and a second write operation, wherein said first read operation comprises reading out the information bits stored in said second storing means, said second read operation comprises reading out the information bits stored in said first storing means, transferring said information bits and said check bits corresponding thereto to said error correcting means, and correcting any error in the information bits and writting the resulting information bits to said second storing means, said first write operation comprises writing information bits to said second storing means and writing said information bits and said check bits generated by said check bit generating means to said first storing means, and said second write operating comprises writing information bits and said check bits generated by said check bit generating means to said first storing means.
Claim 15
Independent Claim
306 words
A method for controlling a semiconductor memory device for storing information bits including, on a single chip, a plurality of bits and check bits used for detecting and correcting an error in both the information bits and the check bits or an error in the information bits, comprising check bit generating means responsive to said information bits for generating said check bits; first storing means for storing a plurality of sets of said information bits and said check bits generated by said check bit generating means; error correcting means for detecting and correcting the error in both said information bits and said check bits or the error in said information bits using said check bits corresponding to said information bits; and second storing means comprising a cache memory having smaller memory capacity than said first storing means, and to which access can be made faster than the access speed to said first storing means, and for storing some of said information bits, comprising: a first read operation, a second read operation, a first write operation and a second write operation, wherein said first read operation comprises reading out the information bits stored in said second storing means, said second read operation comprises reading out the information bits stored in said first storing means, transferring said information bits and said check bits corresponding thereto to said error correcting means, and correcting any error in the information bits and writting the resulting information bits to said second storing means, said first write operation comprises writing information bits to said second storing means and writing said information bits and said check bits generated by said check bit generating means to said first storing means, and said second write operating comprises writing information bits and said check bits generated by said check bit generating means to said first storing means.
References Cited (Backward Citations)
US3814921A
Cited
US4077028A
Cited
US4493081A
Cited
US4703453A
Cited
JPS592300A
Cited
US4617660A
Cited
US4577293A
Cited
US4654847A
Cited
US4791642A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-08-27 | 1994-02-26 | 1994-08-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-08-27 | 1998-02-26 | 1998-08-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-08-27 | 2002-02-26 | 2002-08-28 | $7700.00 | Window Closed / Lapsed |