Faulty-memory processing method and apparatus

Claim 2

A faulty memory processing method in a data processing system including memory means having a normal memory with a plurality of cells for storing information, a relief memory, and error correction means for detecting and correcting an error in information read out from at least one cell in said normal memory, said data processing system executing a time-sharing data process with time period breaks, said faulty-memory processing method comprising the steps of: detecting a hard error which may exist in at least one cell in said normal memory, said detection being carried out using said error correction means; correcting, using said error correction means, an error in information read out from a detected harderror cell of the normal memory; transcribing information including the corrected information with respect to the detected hard-error cell of the normal memory into the relief memory, said correcting and transcribing steps being executed during the time period breaks in said time-sharing data process; and processing in a normal mode where data read out from the memory means are immediately utilized without waiting for the detection and correction performed by the error

Claim 3

A method as claimed in claim 1, wherein said detecting step includes the steps of: correcting an error in information read out from at least one cell in the normal memory by said error correction means; writing the corrected information back in said cell in which the error occurs; reading out information again from said error cell in the normal memory; and detecting an error, by said error correction means, in the information read out again from said error cell.

Claim 4

A method as claimed in claim 1, wherein said memory means further includes refresh means for periodically refreshing a plurality of cells in the normal and relief memories for a predetermined period of time, said correcting and transcribing steps being executed during said refresh period.

Claim 5

A method as claimed in claim 3, wherein said correcting step is started at the start of every refresh period.

Claim 6

A method as claimed in claim 1, further comprising stopping the data processing when an error is detected in the information presently used in the data processing and awaiting detection of a hard error.

Claim 7

A method as claimed in claim 1, wherein said memory means stores a program for controlling data processing of the data processing means, wherein said correcting and transcribing steps are executed without using said program.

Claim 8

A faulty-memory processing apparatus in a data processing system including memory means having a normal memory with a plurality of cells for storing information, a relief memory, and error correction means for detecting and correcting an error in information read out from at least one cell in said normal memory, said data processing system executing a time-sharing data process with time period breaks, indicating the time period breaks and executing an operation using data read out of said memory means during a data error detection and correction operation, said faulty-memory processing apparatus comprising; means for detecting a hard error which may exist in at least one cell in said normal memory, said detection being carried out by using said error correction means during the data operation by said data processing system; means for correcting, by using said error correction means, an error in information read out from a detected hard-error cell of the normal memory and detecting the time period breaks; and means for transcribing information including the corrected information with respect to the detected hard-error cell of the normal memory into the relief memory, said correcting and transcribing being executed during the time period breaks in said time-sharing data process.

Claim 9

A faulty-memory processing apparatus in a data processing system including memory means having a normal memory with a plurality of cells for storing information, a relief memory, and error correction means for detecting and correcting an error in information read out from at least one cell in said normal memory, said data processing system executing a time-sharing data process with time period breaks, indicating the time period breaks and executing an operation using data read out of said memory means during a data error detection and correction operation, said faulty-memory processing apparatus comprising; means for detecting a hard error which may exist in at least one cell in said normal memory, said detection being carried out by using said error correction means during the data operation by said data processing system; means for correcting, by using said error correction means, an error in information read out from a detected hard-error cell of the normal memory and detecting the time period breaks; and means for transcribing information including the corrected information with respect to the detected hard-error cell of the normal memory into the relief memory, said correcting and transcribing being executed during the time period breaks in said time-sharing data process.

Claim 10

An apparatus as claimed in claim 7, wherein said detecting means includes: means for correcting an error in information read out from at least one cell in the normal memory by using said error correction means; means for writing the corrected information back in said cell from which the error occurs; means for reading out information again from said error cell in the normal memory; and means for detecting, by using said error correction means, an error in the information read out again from said error cell.

Claim 11

An apparatus as claimed in claim 7, wherein said memory means further includes refresh means for periodically refreshing a plurality of cells in the normal and relief memories for a predetermined period of time, said correcting and transcribing being executed during said refresh period.

Claim 12

An apparatus as claimed in claim 9, wherein said correcting is started at the start of every refresh period.

Claim 13

An apparatus as claimed in claim 7, wherein said data processing system first executes data processing using information read out from the normal memory of the memory means without waiting for detection of an error which may occur in said information presently used in the data processing.

Claim 14

An apparatus as claimed in claim 11, wherein said data processing system stops the data processing when an error is detected in the information presently used in the data process and awaits detection of a hard error.

Claim 15

An apparatus as claimed in claim 7, wherein said memory means stores a program for controlling data processing by the data processing system, and wherein said correcting and transcribing are executed without using said program.

Claim 16

A memory apparatus for a processor which executes using read-out data during a data error detection and correction operation, the memory apparatus and processor operatively connected to a bus and comprising: memory control means, operatively connected to the bus, for controlling memory refresh and memory transcription and for stopping execution by the processor when an error is detected; an address register operatively connected to the bus; a write data register, operatively connected to the bus, for receiving and storing write data; distribution and selection means, operatively connected to the write data register, for selecting the write data; a normal memory operatively connected to said distribution and selection means; a relief memory operatively connected to said distribution and selection means, said distribution and selection means selecting and applying data to said normal memory or said relief memory, and said relief memory for storing corrected data when a hard error occurs in said normal memory; a first read data register operatively connected to said normal memory; a second read data register operatively connected to said relief memory; selection means, operatively connected to said first and second read data registers, for selecting the data from one of said first and second read data registers; error detecting means, operatively connected to said memory control means and said selection means, for detecting errors in the data from said selection means while the processor is executing using the data; error correction means, operatively connected to said memory control means, said selection means, said error detecting means, said distribution and selection means and the bus, for transferring the data from said selection means to the processor via the bus without correction and for transferring the data from said selection means to said distribution and selection means after correction, said distribution and selection means storing the corrected data in said normal memory; status storage means, operatively connected to said error detecting means, said address register and said memory control means, for storing a type of error detected and a status indicator indicating which of the relief memory or normal memory stores the correct data; and said memory control means controlling the reading out of the corrected data and if the corrected data contains an error, said memory and control means transferring newly corrected data to said relief memory and indicating that said relief memory stores the correct data.

Claim 17

A memory apparatus for a processor which executes using read-out data during a data error detection and correction operation, the memory apparatus and processor operatively connected to a bus and comprising: memory control means, operatively connected to the bus, for controlling memory refresh and memory transcription and for stopping execution by the processor when an error is detected; an address register operatively connected to the bus; a write data register, operatively connected to the bus, for receiving and storing write data; distribution and selection means, operatively connected to the write data register, for selecting the write data; a normal memory operatively connected to said distribution and selection means; a relief memory operatively connected to said distribution and selection means, said distribution and selection means selecting and applying data to said normal memory or said relief memory, and said relief memory for storing corrected data when a hard error occurs in said normal memory; a first read data register operatively connected to said normal memory; a second read data register operatively connected to said relief memory; selection means, operatively connected to said first and second read data registers, for selecting the data from one of said first and second read data registers; error detecting means, operatively connected to said memory control means and said selection means, for detecting errors in the data from said selection means while the processor is executing using the data; error correction means, operatively connected to said memory control means, said selection means, said error detecting means, said distribution and selection means and the bus, for transferring the data from said selection means to the processor via the bus without correction and for transferring the data from said selection means to said distribution and selection means after correction, said distribution and selection means storing the corrected data in said normal memory; status storage means, operatively connected to said error detecting means, said address register and said memory control means, for storing a type of error detected and a status indicator indicating which of the relief memory or normal memory stores the correct data; and said memory control means controlling the reading out of the corrected data and if the corrected data contains an error, said memory and control means transferring newly corrected data to said relief memory and indicating that said relief memory stores the correct data.

Claim 18

A data correction method for data transferred to a processor using primary and relief memories, comprising the steps of: beginning execution using data read from the primary memory; detecting an error in the data read from the primary memory and stopping execution; correcting the error and storing corrected data in the primary memory; detecting an error in the corrected data; correcting the error in the corrected data and storing newly corrected data in the relief memory; indicating that the relief memory stores correct data; and transferring the newly corrected data to the processor and resuming execution.

Claim 19

A data correction method for data transferred to a processor using primary and relief memories, comprising the steps of: beginning execution using data read from the primary memory; detecting an error in the data read from the primary memory and stopping execution; correcting the error and storing corrected data in the primary memory; detecting an error in the corrected data; correcting the error in the corrected data and storing newly corrected data in the relief memory; indicating that the relief memory stores correct data; and transferring the newly corrected data to the processor and resuming execution.