Apparatus for detecting, correcting and logging single bit memory read errors

Claim 1

In a data processing system, the combination comprising: selectively addressable storage means including a plurality of memories; addressing means for addressing a said memory to read out selected memory data therefrom, said selected memory data including a plurality of check bits chosen so as to permit determining whether at least a single bit error is present in the selected memory data; local error detection and correction means, one for each memory, for detecting and correcting single bit memory read errors in selected memory data read from its respective memory in response to said check bits included therein and for automatically restoring corrected memory data back into the respective memory address whenever a single bit memory read error is detected; common error detection and correction means to which data read from each memory is applied without correction by its respective local error detection and correction means, said common error detection and correction means being operative in response to the check bits included in each selected memory data applied thereto to detect and correct single bit errors and to provide a single bit error signal each time a single bit error is detected in applied memory data along with a corresponding error signal pattern indicating the incorrect bit; and selective error determining means constructed and arranged to operate in response to said single bit error signal, said addressing means, and said error signal pattern for indicating when a detected single bit error in data read from a memory is likely to be hardware related by determining whether this same error has been consecutively detected a predetermined plurality of times for the same memory area.