Semiconductor memory device having improved connecting structure of bit line and memory cell

Claim 2

A semiconductor device comprising: a semiconductor substrate comprising a first layer of a first conductivity type having a predetermined impurity concentration, a first insulating layer formed on said first layer of the first conductivity type and a second layer of the first conductivity type having a major surface formed on said first insulating layer, said semiconductor substrate having a trench formed through said first layer of the first conductivity type, said first insulating layer and said second layer of the first conductivity type, a first layer of a second conductivity type formed in a region of said second layer of the first conductivity type and in the sidewall portion of said trench, a second layer of the second conductivity type formed spaced apart, by predetermined spacing, from said first layer of the second conductivity type in said second layer of the first conductivity type, a first conductive layer formed adjacent to said second layer of the second conductivity type in said second layer of the first conductivity type, a third layer of the second conductivity type formed on the sidewall of said trench at least on the side of a portion in which said first layer of the second conductivity type is formed, a second insulating layer formed on the sidewall and in the bottom portion of said trench having said third layer of the second conductivity type formed, a second conductive layer formed on the surface of said third insulating layer on the sidewall and the bottom surface of said trench, said third layer of the second conductivity type, said second insulating layer and said second conductive layer constituting a capacitor of a memory cell, a third insulating layer formed in the upper portion of said trench on said major surface, and a third conductive layer formed on said third insulating layer, said second layer of the first conductivity type, said first layer of the second conductivity type, said second layer of the second conductivity type and said third conductive layer constituting a semiconductor element.

Claim 3

A semiconductor device according to claim 1, wherein said semiconductor element comprises a field effect element.

Claim 4

A semiconductor device according to claim 2, wherein said field effect element comprises a field effect transistor in which said third conductive layer is a gate electrode, said first layer of the second conductivity type and said second layer of the second conductivity type are any of the a drain region and a source region, respectively, and the major surface of said second layer of the first conductivity type interposed between said first layer of the second conductivity type and said second layer of the second conductivity type is a channel region.

Claim 5

A semiconductor device according to claim 3, wherein said semiconductor device comprises a semiconductor memory device.

Claim 6

A semiconductor device comprising: a semiconductor substrate comprising a first layer of a first conductivity type having a predetermined impurity concentration, a first insulating layer formed on said first layer of the first conductivity type and a second layer of the first conductivity type having a major surface formed on said first insulating layer, said semiconductor substrate having a trench formed through said first insulating layer and said second layer of the first conductivity type, a first layer of a second conductivity type formed in a region of said second layer of the first conductivity type and in the sidewall portion of said trench, a second layer of the second conductivity type formed spaced apart, by predetermined spacing, from said first layer of the second conductivity type in said second layer of the first conductivity type, a first conductive layer formed adjacent to said second layer of the second conductivity type in said second layer of the first conductivity type, a third layer of the second conductivity type formed on the sidewall of said first trench at least on the side of a portion in which said first layer of the second conductivity type is formed, a second insulating layer formed on the sidewall and in the bottom portion of said trench having said third layer of the second conductivity type formed, a second conductive layer formed on the surface of said third insulating layer on the sidewall and the bottom surface of said trench, said third layer of the second conductivity type, said second insulating layer and said second conductive layer constituting a capacitor of a memory cell, a third insulating layer formed in the upper portion of said trench on said major surface, and a third conductive layer formed on said fourth insulating layer, said second layer of the first conductivity type, said first layer of the second conductivity type, said second layer of the second conductivity type and said third conductive layer constituting a semiconductor element, said semiconductor element comprising a field effect element, said field effect element comprising a field effect transistor in which said third conductive layer is a gate electrode, said first layer of the second conductivity type and said second layer of the second conductivity type are any of a drain region and a source region, respectively, and the major surface of said second layer of the first conductivity type. interposed between said first layer of the second conductivity type and said second layer of the second conductivity type is a channel region, said semiconductor service comprising a semiconductor memory device, wherein said semiconductor substrate has a second trench formed spaced apart, by predetermined spacing, from said trench in said second layer of the first conductivity type, said second layer of the second conductivity type and said first conductive layer are formed in the sidewall portion of said second trench, and said second insulating layer is formed inside said second trench.

Claim 7

A semiconductor device comprising: a semiconductor substrate comprising a first layer of a first conductivity type having a predetermined impurity concentration, a first insulating layer formed on said first layer of the first conductivity type and a second layer of the first conductivity type having a major surface formed on said first insulating layer, said semiconductor substrate having a trench formed through said first insulating layer and said second layer of the first conductivity type, a first layer of a second conductivity type formed in a region of said second layer of the first conductivity type and in the sidewall portion of said trench, a second layer of the second conductivity type formed spaced apart, by predetermined spacing, from said first layer of the second conductivity type in said second layer of the first conductivity type, a first conductive layer formed adjacent to said second layer of the second conductivity type in said second layer of the first conductivity type, a third layer of the second conductivity type formed on the sidewall of said first trench at least on the side of a portion in which said first layer of the second conductivity type is formed, a second insulating layer formed on the sidewall and in the bottom portion of said trench having said third layer of the second conductivity type formed, a second conductive layer formed on the surface of said third insulating layer on the sidewall and the bottom surface of said trench, said third layer of the second conductivity type, said second insulating layer and said second conductive layer constituting a capacitor of a memory cell, a third insulating layer formed in the upper portion of said trench on said major surface, and a third conductive layer formed on said fourth insulating layer, said second layer of the first conductivity type, said first layer of the second conductivity type, said second layer of the second conductivity type and said third conductive layer constituting a semiconductor element, said semiconductor element comprising a field effect element, said field effect element comprising a field effect transistor in which said third conductive layer is a gate electrode, said first layer of the second conductivity type and said second layer of the second conductivity type are any of a drain region and a source region, respectively, and the major surface of said second layer of the first conductivity type. interposed between said first layer of the second conductivity type and said second layer of the second conductivity type is a channel region, said semiconductor service comprising a semiconductor memory device, wherein said semiconductor substrate has a second trench formed spaced apart, by predetermined spacing, from said trench in said second layer of the first conductivity type, said second layer of the second conductivity type and said first conductive layer are formed in the sidewall portion of said second trench, and said second insulating layer is formed inside said second trench.

Claim 8

A semiconductor device according to claim 5, wherein said semiconductor memory device comprises a plurality of capacitors of said memory cell and a plurality of said field effect transistors, a thick insulating film formed under said trench, and a third layer of the first conductivity type formed under said thick insulating film, whereby said trench is isolated on the bottom surface thereof.

Claim 9

A semiconductor device according to claim 6, said second trench is formed to the depth of said first insulating layer, said second trench is isolated by said second insulating layer and said first insulating layer, so that said second trench is divided into one sidewall region and the other sidewall region, and the first conductive layer is formed in said one sidewall region and a fourth conductive layer is formed in a said other sidewall region.

Claim 10

A memory cell of a dynamic random access memory device having a transistor and a capacitor connected to said transistor, comprising: a semiconductor substrate comprising a first layer of a first conductivity type, a first insulating layer formed on said first layer of the first conductivity type and a second layer of the first conductivity type having a major surface formed on said first insulating layer, said substrate having a first trench and a second trench formed in said second layer of the first conductivity type and spaced apart from the first trench; a first source/drain region of said transistor of a second conductivity type formed on a sidewall of said first trench of said substrate; a second source/drain region of said transistor of a second conductivity type formed on a sidewall of said second trench of said substrate opposing said first source/drain region, said second source/drain region electrically connected to a bit line formed on said sidewall of said second trench; a gate electrode of said transistor formed above the region between the source/drain regions of said transistor with a gate insulator posed therebetween; a first electrode of said capacitor formed electrically connected to said first source/drain region on said sidewall of said first trench; and a second electrode of said capacitor formed on said first electrode in said first trench with an insulator posed therebetween.

Claim 11

A memory cell of a dynamic random access memory device having a transistor and a capacitor connected to said transistor, comprising: a semiconductor substrate comprising a first layer of a first conductivity type, a first insulating layer formed on said first layer of the first conductivity type and a second layer of the first conductivity type having a major surface formed on said first insulating layer, said substrate having a first trench and a second trench formed in said second layer of the first conductivity type and spaced apart from the first trench; a first source/drain region of said transistor of a second conductivity type formed on a sidewall of said first trench of said substrate; a second source/drain region of said transistor of a second conductivity type formed on a sidewall of said second trench of said substrate opposing said first source/drain region, said second source/drain region electrically connected to a bit line formed on said sidewall of said second trench; a gate electrode of said transistor formed above the region between the source/drain regions of said transistor with a gate insulator posed therebetween; a first electrode of said capacitor formed electrically connected to said first source/drain region on said sidewall of said first trench; and a second electrode of said capacitor formed on said first electrode in said first trench with an insulator posed therebetween.

Claim 12

A dynamic random access memory array including a plurality of memory cells, each cell having a transistor and capacitor connected to said transistor and comprising: a semiconductor substrate comprising a first layer of a first conductivity type, a first insulating layer formed on said first layer of the first conductivity type and a second layer of the first conductivity type having a major surface formed on said first insulating layer, said substrate having a first trench and a second trench formed in said second layer of the first conductivity type and spaced apart from the first trench; a first source/drain region of said transistor of a second conductivity type formed on a sidewall of said first trench of said substrate; a second source/drain region of said transistor of a second conductivity type formed on a sidewall of said second trench of said substrate opposing said first source/drain region, said second source/drain region electrically connected to a bit line formed on a sidewall of said second trench; gate electrode of said transistor formed above the region between the source/drain regions of said transistor with a gate insulator posed therebetween; a first electrode of said capacitor formed electrically connected to said first source/drain region on said sidewall of said first trench; a second electrode of said capacitor formed on said first electrode in said first trench with an insulator posed therebetween; wherein said bit line extends through a substrate plane in a direction parallel to said first trench; and said gate electrode is a portion of a word line that extends in a plane overlying said substrate plane and in a direction perpendicular to said bit line.

Claim 13

A dynamic random access memory array including a plurality of memory cells, each cell having a transistor and capacitor connected to said transistor and comprising: a semiconductor substrate comprising a first layer of a first conductivity type, a first insulating layer formed on said first layer of the first conductivity type and a second layer of the first conductivity type having a major surface formed on said first insulating layer, said substrate having a first trench and a second trench formed in said second layer of the first conductivity type and spaced apart from the first trench; a first source/drain region of said transistor of a second conductivity type formed on a sidewall of said first trench of said substrate; a second source/drain region of said transistor of a second conductivity type formed on a sidewall of said second trench of said substrate opposing said first source/drain region, said second source/drain region electrically connected to a bit line formed on a sidewall of said second trench; gate electrode of said transistor formed above the region between the source/drain regions of said transistor with a gate insulator posed therebetween; a first electrode of said capacitor formed electrically connected to said first source/drain region on said sidewall of said first trench; a second electrode of said capacitor formed on said first electrode in said first trench with an insulator posed therebetween; wherein said bit line extends through a substrate plane in a direction parallel to said first trench; and said gate electrode is a portion of a word line that extends in a plane overlying said substrate plane and in a direction perpendicular to said bit line.