Patent US4952824A successfully refreshed from Google Patents.
US4952824A
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US
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Ion implantation programmable logic device
Assignee: Sharp Corp
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Filing: 1988-10-07
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Granted: 1990-08-28
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Expires: 2008-10-07
Abstract
Abstract A programmable logic device includes logic cells with input signal circuits for each of the logic cells. In the input circuits first MOS transistors are connected in series or parallel and one end of each of the input signal circuits is connected to one of the inputs of the logic cells. There are also signal lines, each of which interconnects the gates of the first transistors. Output signal circuits have second MOS transistors, each of which is connected to the signal lines, the gates of the second transistors being connected to the outputs of the logic cells. The channels of the first and second transistors can be ion-implanted so that the threshold level of the MOS transistors can be changed.
Inventors
- 👤 Setsufumi Kamuro
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 12:33
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/1778; H03K19/1733; H03K19/1735; H03K19/17704; H03K19/17724; H03K19/17728; H10; H10B; H10B20/00
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
173 words
A programmable logic device comprising: at least one logic cell having at least one input and at least one output; at least one input signal circuit for each of said at least one logic cell, said at least one input signal circuit having first MOS transistors connected in series, one end of each of said at least one input signal circuit being connected to at least one of said inputs of said at least one logic cell, the other end of each of said at least one input signal circuit being connected to one voltage level; signal lines, each of which interconnects the gates of corresponding ones of said MOS transistors; load elements connected between each of said signal lines and another voltage level; and at least one output signal circuit having second MOS transistors each of which is connected between another voltage level and one of said signal lines, respectively, the gates of said second MOS transistors being connected to said at least one output of said at least one logic cell.
Claim 2
Dependent Claim
173 words
A programmable logic device comprising: at least one logic cell having at least one input and at least one output; at least one input signal circuit for each of said at least one logic cell, said at least one input signal circuit having first MOS transistors connected in series, one end of each of said at least one input signal circuit being connected to at least one of said inputs of said at least one logic cell, the other end of each of said at least one input signal circuit being connected to one voltage level; signal lines, each of which interconnects the gates of corresponding ones of said MOS transistors; load elements connected between each of said signal lines and another voltage level; and at least one output signal circuit having second MOS transistors each of which is connected between another voltage level and one of said signal lines, respectively, the gates of said second MOS transistors being connected to said at least one output of said at least one logic cell.
Claim 3
Dependent Claim
16 words
A device according to claim 1, wherein said first and second MOS transistors are NMOS transistors.
Claim 4
Dependent Claim
16 words
A device according to claim 1, wherein said first and second MOS transistors are PMOS transistors.
Claim 5
Dependent Claim
25 words
A device according to claim 1, wherein said first and second MOS transistors are programmably conductive by means of ion implantation in their respective channels.
Claim 6
Dependent Claim
20 words
A device according to claim 1, wherein no metal layer is disposed above both said first and second MOS transistors.
Claim 7
Dependent Claim
179 words
A programmable logic device comprising: at least one logic cell having at least one input and at least one output; at least one input signal circuit for each of said at least one logic cell, said at least one input signal circuit having first MOS transistors of one type connected in parallel, one end of each of said at least one input signal circuit being connected to at least one of said input of said at least one logic cell, the other end of each of said input signal circuits being connected to one voltage level; signal lines, each of which interconnects the gates of corresponding ones of said first MOS transistors; load elements connected between each of said signal lines and another voltage level; and at least one output signal circuit having second MOS transistors of the opposite conductivity type, each of which is connected between another voltage level and one of said signal lines, respectively, the gates of said second MOS transistors being connected to said at least one output of said at least one logic cell.
Claim 8
Dependent Claim
179 words
A programmable logic device comprising: at least one logic cell having at least one input and at least one output; at least one input signal circuit for each of said at least one logic cell, said at least one input signal circuit having first MOS transistors of one type connected in parallel, one end of each of said at least one input signal circuit being connected to at least one of said input of said at least one logic cell, the other end of each of said input signal circuits being connected to one voltage level; signal lines, each of which interconnects the gates of corresponding ones of said first MOS transistors; load elements connected between each of said signal lines and another voltage level; and at least one output signal circuit having second MOS transistors of the opposite conductivity type, each of which is connected between another voltage level and one of said signal lines, respectively, the gates of said second MOS transistors being connected to said at least one output of said at least one logic cell.
Claim 9
Dependent Claim
24 words
A device according to claim 6, wherein said first MOS transistors are of the N-type, and said second MOS transistors are of the P-type.
Claim 10
Dependent Claim
22 words
A device according to claim 6, wherein said first MOS transistors are the P-type, and said second MOS transistors are the N-type.
Claim 11
Dependent Claim
25 words
A device according to claim 6, wherein said first and second MOS transistors are programmably conductive by means of ion implantation in their respective channels.
Claim 12
Dependent Claim
38 words
A device according to claim 6, wherein no metal layer is disposed above both said first and second MOS transistors, said first and second MOS transistors are programmably conductive by means of ion implantation in their respective channels.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-08-27 | 1994-02-26 | 1994-08-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-08-27 | 1998-02-26 | 1998-08-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-08-27 | 2002-02-26 | 2002-08-28 | $7700.00 | Window Closed / Lapsed |