US4644191A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Programmable array logic with shared product terms
Assignee: Intersil Corp
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Filing: 1985-09-19
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Granted: 1987-02-17
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Expires: 2005-09-19
Abstract
Abstract A programmable logic circuit comprises a Programmable Array Logic (PAL) circuit in which individual product terms may be shared simultaneously by one or more of the circuit outputs. The product terms are selectively connected to the circuit outputs by programmable elements (such as a fusible link) to increase design flexibility. Isolating devices are provided in series with the programmable elements to allow for the simultaneous product term sharing.
Inventors
- 👤 Barbara J. Fisher
- 👤 Ian E. Harvey
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 03:30
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/17704; H03K19/17708
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
111 words
A programmable logic circuit, comprising: an array having a plurality of inputs and plurality of outputs and means for combining selected ones of said inputs at each of said outputs; logic means for selectively connecting a first set of said array outputs to a first one of a plurality of programmable logic circuit outputs; logic means for selectively connecting a second set of said array outputs to a second programmable logic circuit output; wherein, said first set of array outputs includes less than all of said array outputs and, wherein said first set of array outputs includes at least one array output in common with said second set of array outputs.
Claim 2
Dependent Claim
111 words
A programmable logic circuit, comprising: an array having a plurality of inputs and plurality of outputs and means for combining selected ones of said inputs at each of said outputs; logic means for selectively connecting a first set of said array outputs to a first one of a plurality of programmable logic circuit outputs; logic means for selectively connecting a second set of said array outputs to a second programmable logic circuit output; wherein, said first set of array outputs includes less than all of said array outputs and, wherein said first set of array outputs includes at least one array output in common with said second set of array outputs.
Claim 3
Dependent Claim
23 words
A programmable logic circuit according to claim 1, wherein said second set of array outputs includes less than all of said array outputs.
Claim 4
Dependent Claim
15 words
A programmable logic circuit according to claim 1, wherein said array is an AND array.
Claim 5
Dependent Claim
42 words
A programmable logic circuit according to claim 1, wherein said means for connecting each of said array outputs to said logic circuit outputs comprises a programmable logic element serially connected to means for electrically isolating said first and second logic circuit outputs.
Claim 6
Dependent Claim
44 words
A programmable logic circuit according to claim 4, wherein said isolation means includes a three-terminal device having a first terminal connected to said programmable element, a second terminal connected to a power source and a third terminal connected to one of said array outputs.
Claim 7
Dependent Claim
23 words
A programmable logic circuit according to claim 5, wherein said three-terminal device is a transistor and said third terminal is a control terminal.
Claim 8
Dependent Claim
133 words
A programmable logic circuit, comprising: an array having a plurality of inputs for receiving input terms and a plurality of array outputs and means for combining selected ones of said input terms at each of said array outputs; means for connecting a first array output to a first one of a plurality of outputs of said programmable logic circuit; means for connecting a second array output to a second programmable logic circuit output; and means for selectively connecting a third array output to either or both of said first and second programmable logic circuit outputs; wherein said selective connection means includes logic means, having inputs connected to the array outputs, and outputs which are connected to the programmable logic circuit outputs, for selectively combining the array outputs at said programmable logic circuit outputs.
Claim 9
Dependent Claim
133 words
A programmable logic circuit, comprising: an array having a plurality of inputs for receiving input terms and a plurality of array outputs and means for combining selected ones of said input terms at each of said array outputs; means for connecting a first array output to a first one of a plurality of outputs of said programmable logic circuit; means for connecting a second array output to a second programmable logic circuit output; and means for selectively connecting a third array output to either or both of said first and second programmable logic circuit outputs; wherein said selective connection means includes logic means, having inputs connected to the array outputs, and outputs which are connected to the programmable logic circuit outputs, for selectively combining the array outputs at said programmable logic circuit outputs.
Claim 10
Dependent Claim
29 words
A programmable logic circuit according to claim 7, wherein said array is a product term generator and said combinations of input terms at said array outputs are product terms.
Claim 11
Dependent Claim
42 words
A programmable logic circuit according to claim 7, wherein said means for connecting each of said array outputs to said programmable logic circuit outputs comprises a programmable element serially connected to means for electrically isolating said first and second logic circuit outputs.
Claim 12
Dependent Claim
44 words
A programmable logic circuit according to claim 9, wherein said isolation means includes a three-terminal device having a first terminal connected to said programmable element, a second terminal connected to a power source and a third terminal connected to one of said array outputs.
Claim 13
Dependent Claim
23 words
A programmable logic circuit according to claim 10, wherein said three-terminal device is a transistor and said third terminal is a control terminal.
References Cited (Backward Citations)
US3975623A
Cited
US4124899A
Cited
US4124899B1
Cited
US4245324A
Cited
US4433331A
Cited
US4409499A
Cited
US4554640A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-02-16 | 1990-08-18 | 1991-02-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-02-16 | 1994-08-18 | 1995-02-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-02-16 | 1998-08-18 | 1999-02-17 | $7700.00 | Window Closed / Lapsed |