Semiconductor memeory device in which writing is inhibited in address skew period and controlling method thereof

Claim 2

A semiconductor memory device comprising: a plurality of memory cells, selecting means responsive to a plurality of column line and row line address signals externally applied for selecting any of said plurality of memory cells, corresponding column line and row line address signals being offset in time by an address skew time period, writing means for writing data to a memory cell selected by said selecting means, a plurality of address transition detecting means responsive to each of said plurality of column line and row line signals for generating one-shot pulses, first signal generating means responsive to the one-shot pulses from said plurality of address transition detecting means for generating a first pulse signal, second signal generating means responsive to said first pulse signal for increasing the pulse width of said first pulse signal to exceed said address skew time period and outputting the same as a second signal, and write inhibiting means responsive to said second signal from said second signal generating means for rendering said writing means inactive during second signal pulse.

Claim 3

A semiconductor memory device according to claim 1, which further comprises at least one bit line pair connected to each cell of said plurality of memory cells, and equalizing means responsive to said first signal from said first signal generating means for equalizing potentials of said at least one bit line pair.

Claim 4

A semiconductor memory device according to claim 1, which further comprises: a plurality of bit line pairs each connected to a cell group of said plurality of memory cells, a pair of input/output lines selectively coupled to one pair, of said plurality of bit line pairs, and equalizing means responsive to said first signal from said first potential generating means for equalizing potentials of said pair of input/output lines.

Claim 5

A semiconductor memory device according to claim 1, which further comprises a plurality of bit line pairs each connected to a cell group of said plurality of memory cells, a pair of input/output lines selectively coupled to one pair, of said plurality of bit line pairs, a sense amplifier for amplifying the potential difference between said pair of input/output lines, a data bus coupled to an output from said sense amplifier, and precharging means responsive to said first signal from said first said first signal generating means for precharging said data bus to a predetermined potential.

Claim 6

A semiconductor memory device according to claim 1, wherein said first signal generating means comprises logical sum means for ORing said one-shot pulses from said plurality of address transition detecting means.

Claim 7

A semiconductor memory device according to claim 1, wherein said second signal generating means comprises an input terminal coupled to said first pulse signal, delay means for outputting a signal which changes from a first logical level to a second logical level in response to the start of said first signal applied to said input terminal while changing gently from said second logical level to said first logical level in response to the end of said first signal, and inverting means for inverting said signal outputted from said delay means.

Claim 8

A semiconductor memory device according to claim 6, wherein said delay means comprises a node connected to said inverting means, a plurality of field effect elements each having a first conductivity type channel, said elements coupled in series between a potential of said first logical level and said node and each of said elements having a gate connected to said input terminal, a field effect element having a second conductivity type channel and coupled between a potential of said second logical level and said node and having a gate connected to said input terminal, and capacitance means coupled between the potential of said second logical level and said node.

Claim 9

A semiconductor memory device according to claim 1, which further comprises inhibit releasing signal generating means responsive to the start of a write enable signal externally applied for generating an inhibit releasing signal having a predetermined pulse width, said write inhibiting means rendering said writing means active in response to said inhibit releasing signal and the end of said first signal while rendering said writing means inactive in response to the end of said write enable signal.

Claim 10

A semiconductor memory device according to claim 8, wherein the pulse width of said inhibit releasing signal is larger than the pulse width of said second signal.

Claim 11

A semiconductor memory device according to claim 1, wherein each of said plurality of memory cells comprises a static type memory cell.

Claim 12

A semiconductor memory device comprising: a plurality of memory cells, selecting means responsive to a plurality of column line and row line address signals externally applied for selecting any of said plurality of memory cells, corresponding column line and row line address signals being offset in time by an address skew time period, writing means for writing data to a memory cell selected by said selecting means, a plurality of address transition detecting means responsive to each of said plurality of column line and row line signals for generating one-shot pulses, first signal generating means responsive to the one-shot pulses from said plurality of address transition detecting means for generating a first pulse signal, second signal generating means responsive to said first pulse signal for increasing the pulse width of said first pulse signal to exceed said address skew time period and outputting the same as a second pulse signal, write inhibiting means responsive to said second pulse signal from said second signal generating means for rendering said writing means inactive during the second pulse signal, inhibit releasing signal generating means responsive to the start of a write enable signal externally applied for generating an inhibit releasing signal having a predetermined pulse width, said write inhibiting means rendering said writing means active in response to said inhibit releasing signal and the end of said first pulse signal while rendering said writing means inactive in response to the end of said write enable signal, delay means for generating a signal which changes from a first logical level to a second logical level after delay of a predetermined time period from the start of said write enable signal while changing from said second logical level to said first logical level in response to the end of said write enable signal, and logical sum means for ORing said write enable signal and said first logical level of said signal from said delay means to output the same as said inhibit releasing signal.

Claim 13

A semiconductor memory device comprising: a plurality of memory cells, selecting means responsive to a plurality of column line and row line address signals externally applied for selecting any of said plurality of memory cells, corresponding column line and row line address signals being offset in time by an address skew time period, writing means for writing data to a memory cell selected by said selecting means, a plurality of address transition detecting means responsive to each of said plurality of column line and row line signals for generating one-shot pulses, first signal generating means responsive to the one-shot pulses from said plurality of address transition detecting means for generating a first pulse signal, second signal generating means responsive to said first pulse signal for increasing the pulse width of said first pulse signal to exceed said address skew time period and outputting the same as a second pulse signal, write inhibiting means responsive to said second pulse signal from said second signal generating means for rendering said writing means inactive during the second pulse signal, inhibit releasing signal generating means responsive to the start of a write enable signal externally applied for generating an inhibit releasing signal having a predetermined pulse width, said write inhibiting means rendering said writing means active in response to said inhibit releasing signal and the end of said first pulse signal while rendering said writing means inactive in response to the end of said write enable signal, delay means for generating a signal which changes from a first logical level to a second logical level after delay of a predetermined time period from the start of said write enable signal while changing from said second logical level to said first logical level in response to the end of said write enable signal, and logical sum means for ORing said write enable signal and said first logical level of said signal from said delay means to output the same as said inhibit releasing signal.

Claim 14

A semiconductor memory device comprising: a plurality of memory cells, selecting means responsive to a plurality of column line and row line address signals externally applied for selecting any of said plurality of memory cells, corresponding column line and row line address signals being offset in time by an address skew time period, writing means for writing data to a memory cell selected by said selecting means, a plurality of address transition detecting means responsive to each of said plurality of column line and row line signals for generating one-shot pulses, first signal generating means responsive to the one-shot pulses from said plurality of address transition detecting means for generating a first pulse signal, second signal generating means responsive to said first pulse signal for increasing the pulse width of said first pulse signal to exceed said address skew time period and outputting the same as a second pulse signal, write inhibiting means responsive to said second pulse signal from said second signal generating means for rendering said writing means inactive during the second pulse signal, inhibit releasing signal generating means responsive to the start of a write enable signal externally applied for generating an inhibit releasing signal having a predetermined pulse width, said write inhibiting means rendering said writing means active in response to said inhibit releasing signal and the end of said first pulse signal while rendering said writing means inactive in response to the end of said write enable signal, first logical product means for ANDing an inverted signal of said inhibit releasing signal and said second signal, logical sum means for ORing an output of said first logical product means and said first pulse signal, and second logical product means for ANDing an inverted signal of an output of said logical sum means and said write enable signal to output the same as an internal write enable signal, said writing means operating in response to said internal write enable signal.

Claim 15

A semiconductor memory device comprising: a plurality of memory cells, selecting means responsive to a plurality of column line and row line address signals externally applied for selecting any of said plurality of memory cells, corresponding column line and row line address signals being offset in time by an address skew time period, writing means for writing data to a memory cell selected by said selecting means, a plurality of address transition detecting means responsive to each of said plurality of column line and row line signals for generating one-shot pulses, first signal generating means responsive to the one-shot pulses from said plurality of address transition detecting means for generating a first pulse signal, second signal generating means responsive to said first pulse signal for increasing the pulse width of said first pulse signal to exceed said address skew time period and outputting the same as a second pulse signal, write inhibiting means responsive to said second pulse signal from said second signal generating means for rendering said writing means inactive during the second pulse signal, inhibit releasing signal generating means responsive to the start of a write enable signal externally applied for generating an inhibit releasing signal having a predetermined pulse width, said write inhibiting means rendering said writing means active in response to said inhibit releasing signal and the end of said first pulse signal while rendering said writing means inactive in response to the end of said write enable signal, first logical product means for ANDing an inverted signal of said inhibit releasing signal and said second signal, logical sum means for ORing an output of said first logical product means and said first pulse signal, and second logical product means for ANDing an inverted signal of an output of said logical sum means and said write enable signal to output the same as an internal write enable signal, said writing means operating in response to said internal write enable signal.

Claim 18

The method according to claim 13, which further comprises the steps of: generating an inhibit releasing signal having a predetermined pulse width in response to the start of a write enable signal externally applied, and rendering said writing means active in response to said inhibit releasing signal and the end of said first signal while rendering said writing means inactive in response to the end of said write enable signal.

Claim 19

A static semiconductor memory device comprising: a plurality of word lines, a plurality of bit line pairs arranged intersecting with said plurality of word lines, a plurality of memory cells each provided at each of intersections of said plurality of word lines and said plurality of bit line pairs, an X decoder responsive to a plurality of X address signals for selecting any of said plurality of word lines, a Y decoder responsive to a plurality of Y address signals for selecting any of said plurality of bit line pairs, said X address signals and Y address signals being offset in time by an address skew time period, writing means for writing data to a memory cell provided at an intersection of a word line selected by said X decoder and a bit line pair selected by said Y decoder, reading means for reading out data to be stored in the memory cell provided at the intersection of the word line selected by said X decoder and the bit line pair selected by said Y decoder, a plurality of address transition detecting means responsive to said plurality of X address signals or said plurality of Y address signals for generating a plurality of one-shot pulses, first signal generating means responsive to the one-shot pulses from said plurality of address transition detecting means for generating a first signal, second signal generating means responsive to said first signal from said first signal generating means for increasing the pulse width to exceed said address skew time period of said first signal and outputting the same as a second signal, and control means for rendering said writing means active when a write enable signal is applied from the exterior and said second signal is not applied while rendering said reading means active when said write enable signal is not applied.

Claim 20

A static semiconductor memory device comprising: a plurality of word lines, a plurality of bit line pairs arranged intersecting with said plurality of word lines, a plurality of memory cells each provided at each of intersections of said plurality of word lines and said plurality of bit line pairs, an X decoder responsive to a plurality of X address signals for selecting any of said plurality of word lines, a Y decoder responsive to a plurality of Y address signals for selecting any of said plurality of bit line pairs, said X address signals and Y address signals being offset in time by an address skew time period, writing means for writing data to a memory cell provided at an intersection of a word line selected by said X decoder and a bit line pair selected by said Y decoder, reading means for reading out data to be stored in the memory cell provided at the intersection of the word line selected by said X decoder and the bit line pair selected by said Y decoder, a plurality of address transition detecting means responsive to said plurality of X address signals or said plurality of Y address signals for generating a plurality of one-shot pulses, first signal generating means responsive to the one-shot pulses from said plurality of address transition detecting means for generating a first signal, second signal generating means responsive to said first signal from said first signal generating means for increasing the pulse width to exceed said address skew time period of said first signal and outputting the same as a second signal, and control means for rendering said writing means active when a write enable signal is applied from the exterior and said second signal is not applied while rendering said reading means active when said write enable signal is not applied.

Claim 21

A static semiconductor memory device comprising: a plurality of word lines, a plurality of bit line pairs arranged intersecting with said plurality of word lines, a plurality of memory cells each provided at each of intersections of said plurality of word lines and said plurality of bit line pairs, an X decoder responsive to a plurality of X address signals for selecting any of said word lines, a Y decoder responsive to the plurality of Y address signals for selecting any of said plurality of bit line pairs, writing means for writing data to a memory cell provided at an intersection of a word line selected by said X decoder and a bit line pair selected by said Y decoder, reading means for reading out data to be stored in the memory cell provided at the intersection of the word line selected by said X decoder and the bit line pair selected by said Y decoder, a plurality of address transition detecting means responsive to said plurality of X address signals and said plurality of Y address signals for generating one-shot pulses, first signal generating means responsive to the one-shot pulses from said plurality of address transition detecting means for generating a first signal pulse, second signal generating means responsive to said first signal pulse from said first signal generating means for increasing the pulse width of said first signal pulse and outputting the same as a second signal pulse, and inhibit releasing signal generating means responsive to the start of a write enable signal pulse externally applied for generating an inhibit releasing signal pulse having a predetermined pulse width, and control means responsive to said first signal pulse, said second signal pulse, said inhibit releasing signal pulse and said write enable signal pulse for selectively rendering said writing means and said reading means active, said control means rendering said reading means active when said write enable signal pulse is present and said second signal pulse is absent, rendering said writing means inactive when said write enable signal pulse and said second signal pulse are present and said inhibit releasing signal pulse is absent, rendering said writing means active when said write enable signal pulse, said second signal pulse and said inhibit releasing signal pulse are present and said first signal pulse is absent, and rendering said writing means inactive when said write enable signal pulse, said second signal pulse, said inhibit releasing signal pulse and said first signal pulse are present.

Claim 22

A static semiconductor memory device comprising: a plurality of word lines, a plurality of bit line pairs arranged intersecting with said plurality of word lines, a plurality of memory cells each provided at each of intersections of said plurality of word lines and said plurality of bit line pairs, an X decoder responsive to a plurality of X address signals for selecting any of said word lines, a Y decoder responsive to the plurality of Y address signals for selecting any of said plurality of bit line pairs, writing means for writing data to a memory cell provided at an intersection of a word line selected by said X decoder and a bit line pair selected by said Y decoder, reading means for reading out data to be stored in the memory cell provided at the intersection of the word line selected by said X decoder and the bit line pair selected by said Y decoder, a plurality of address transition detecting means responsive to said plurality of X address signals and said plurality of Y address signals for generating one-shot pulses, first signal generating means responsive to the one-shot pulses from said plurality of address transition detecting means for generating a first signal pulse, second signal generating means responsive to said first signal pulse from said first signal generating means for increasing the pulse width of said first signal pulse and outputting the same as a second signal pulse, and inhibit releasing signal generating means responsive to the start of a write enable signal pulse externally applied for generating an inhibit releasing signal pulse having a predetermined pulse width, and control means responsive to said first signal pulse, said second signal pulse, said inhibit releasing signal pulse and said write enable signal pulse for selectively rendering said writing means and said reading means active, said control means rendering said reading means active when said write enable signal pulse is present and said second signal pulse is absent, rendering said writing means inactive when said write enable signal pulse and said second signal pulse are present and said inhibit releasing signal pulse is absent, rendering said writing means active when said write enable signal pulse, said second signal pulse and said inhibit releasing signal pulse are present and said first signal pulse is absent, and rendering said writing means inactive when said write enable signal pulse, said second signal pulse, said inhibit releasing signal pulse and said first signal pulse are present.