US4337523A
Expired / Lapsed
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Bipolar memory circuit
Assignee: Hitachi Ltd
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Filing: 1980-06-09
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Granted: 1982-06-29
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Expires: 2000-06-09
Abstract
Abstract A bipolar memory circuit is provided with a delay circuit which receives a write enabling signal, a gate circuit which detects the coincidence between an input signal and an output signal of the delay circuit, and a circuit which is started by an output signal of the gate circuit and which provides a pulse signal of a fixed time. The operation of a write driver circuit in the bipolar memory circuit is controlled by the pulse signal. Noise interfering in the write enabling signal are neglected by the use of the delay circuit and the gate circuit. The pulse width of the write enabling signal is permitted to be made smaller than the pulse width of the pulse signal required by the write driver circuit.
Inventors
- 👤 Atsuo Hotta
- 👤 Yukio Kato
- 👤 Teruo Isobe
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 12:21
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/413; G11C11/414; G11C7/00; G11C7/22
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
102 words
A bipolar memory circuit comprising: a plurality of memory cells, an address decoder which receives an address signal and which provides a signal for selecting one of the plurality of memory cells corresponding to the address signal, a pulse generator which is started by a write enabling signal and which provides a pulse signal having a fixed pulse duration, and a gate circuit which receives an input data signal and the pulse signal and which provides a write pulse signal corresponding to the input data signal to be written into the selected memory cell, for a period determined by said pulse signal.
Claim 2
Dependent Claim
102 words
A bipolar memory circuit comprising: a plurality of memory cells, an address decoder which receives an address signal and which provides a signal for selecting one of the plurality of memory cells corresponding to the address signal, a pulse generator which is started by a write enabling signal and which provides a pulse signal having a fixed pulse duration, and a gate circuit which receives an input data signal and the pulse signal and which provides a write pulse signal corresponding to the input data signal to be written into the selected memory cell, for a period determined by said pulse signal.
Claim 3
Dependent Claim
69 words
A bipolar memory circuit according to claim 1, wherein said pulse generator is constructed of a first delay circuit which receives said write enabling signal, a gate circuit which receives said write enabling signal and an output signal of said first delay circuit, and a first circuit which is started by an output signal of said gate circuit and which provides said pulse signal having the fixed pulse duration.
Claim 4
Dependent Claim
73 words
A bipolar memory circuit according to claim 2, wherein said first circuit is constructed of a second delay circuit which receives said output signal of said gate circuit, and a flip-flop circuit which has first and second stable statuses, which is brought into the first stable status by said output signal of said gate circuit and which is brought into the second stable status by an output signal of said second delay circuit.
Claim 5
Dependent Claim
37 words
A bipolar memory circuit according to claim 1, further comprising a logic circuit which receives said write enabling signal and a chip enabling signal, said pulse generator being started by an output signal of said logic circuit.
Claim 6
Dependent Claim
37 words
A bipolar memory circuit according to claim 2, further comprising an output buffer circuit which receives a signal provided from the selected memory cell, said output buffer circuit having its operation controlled by said write enabling signal.
Claim 7
Dependent Claim
180 words
A bipolar memory circuit comprising: a plurality of memory cells, an address decoder which receives an address signal and which provides a signal for selecting one of the plurality of memory cells corresponding to the address signal, a pulse generator which receives a write enabling signal and which provides a pulse signal corresponding to the write enabling signal, a gate circuit which receives an input data signal and the pulse signal and which provides a write pulse signal corresponding to the input data signal to be written into the selected memory cell, for a period determined by said pulse signal, an output buffer circuit which receives a signal provided from the selected memory cell and a control signal which provides a signal corresponding to the signal provided from the memory cell, for a period determined by the control signal, and a delay circuit which forms an output signal delayed with respect to an input signal thereof, an operating timing of said pulse generator and that of said output buffer circuit being made different from each other by said delay circuit.
Claim 8
Dependent Claim
180 words
A bipolar memory circuit comprising: a plurality of memory cells, an address decoder which receives an address signal and which provides a signal for selecting one of the plurality of memory cells corresponding to the address signal, a pulse generator which receives a write enabling signal and which provides a pulse signal corresponding to the write enabling signal, a gate circuit which receives an input data signal and the pulse signal and which provides a write pulse signal corresponding to the input data signal to be written into the selected memory cell, for a period determined by said pulse signal, an output buffer circuit which receives a signal provided from the selected memory cell and a control signal which provides a signal corresponding to the signal provided from the memory cell, for a period determined by the control signal, and a delay circuit which forms an output signal delayed with respect to an input signal thereof, an operating timing of said pulse generator and that of said output buffer circuit being made different from each other by said delay circuit.
Claim 9
Dependent Claim
29 words
A bipolar memory circuit according to claim 6, wherein the control signal to be supplied to said output buffer circuit has its changing rate limited by an integration circuit.
Claim 10
Dependent Claim
19 words
A bipolar memory circuit according to claim 6, said bipolar memory circuit being operated by a single power supply.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1985-06-28 | 1985-12-28 | 1986-06-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1989-06-28 | 1989-12-28 | 1990-06-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1993-06-28 | 1993-12-28 | 1994-06-29 | $7700.00 | Window Closed / Lapsed |