Apparatus and method for synchronization of a coprocessor unit in a pipelined central processing unit

Claim 2

A pipelined central processing unit capable of executing a first set of instructions and a plurality of special instructions, said central processing unit comprising: an instruction cache memory unit for storing instructions to be executed; an instruction register for processing an executing instruction from said instruction cache memory unit, said executing instruction being a next instruction to be executed by said central processing unit, said instruction register including means for determining when an executing instruction is a special instruction; an operand cache memory unit for storing operands to be processed; at least one operand register for storing an operand to be processed in response to said executing instruction, wherein said operand to be processed is transferred from said operand cache memory unit to said operand register in response to said executing instruction; an arithmetic logic unit coupled to said instruction register and to said operand register for performing an operation on said operand to be processed in a manner determined by said executing instruction when said executing instruction is selected from said first set of instructions; a coprocessor unit coupled to said instruction register and to said operand register for performing an operation on said operand to be processed in a manner determined by said executing instruction when said executing instruction is a one of said special instructions; storage means coupled to said coprocessor unit for storing a resulting operand provided by said coprocessor unit; first means coupled to said storage means and responsive to a presence of said resulting operand stored in said storage means for applying a first signal to said instruction register; and second means coupled to said instruction register and responsive to said first signal for preventing processing of an executing instruction when said executing instruction is a special instruction until said first signal is present.

Claim 3

The pipelined central processing unit of claim 1 wherein said executing instruction is processed in a manner determined by said executing instruction when said first signal is applied to said second means and said executing instruction is an instruction selected from said first set of instructions.

Claim 4

The pipelined central processing unit of claim 2 wherein an operand to be processed is stored in two locations of said operand cache memory unit and an associated executing special instruction performs an operation selected from the group consisting of a floating point operation and a double precision operation.

Claim 5

The pipelined central processing unit of claim 1 wherein said coprocessor unit executes a one of said special instructions providing an arithmetic operation involving operands and a quantity stored in said coprocessor unit.

Claim 6

The pipelined central processing unit of claim 1 wherein said coprocessor unit executes a special instruction resulting in an operation selected from a group consisting of an integer multiplication operation, integer division operation, a floating point processing operation, and a double precision operation operation.

Claim 7

The pipelined central processing unit of claim 1 wherein said storage means is an accumulator register, said second means preventing processing activity by said coprocessor unit when said resulting operand resulting from a previous sequential special instruction is not stored in said accumulator register.

Claim 8

The pipelined central processing unit of claim 1 wherein said operand cache memory unit is coupled to said instruction register and said operand register, said operand cache memory unit and said instruction register forming a pipeline stage of said pipelined central processing unit.

Claim 9

The pipelined central processing unit of claim 7 wherein a resulting operand stored in said coprocessor unit, provided as a result of a first special instruction being an executing instruction, is stored in said operand cache unit at a location determined by a next sequential special instruction.

Claim 10

The pipelined central processing unit of claim 8 further comprising a multiplexor coupled to said arithmetic logic unit and said coprocessor unit for selecting a resulting operand to be stored in said operand cache memory unit, said resulting operand from said coprocessor unit being stored in said operand cache memory unit when said first signal is present and said executing instruction in said instruction register is a special instruction.

Claim 13

The method of executing regular and special instructions of claim 10 further including the step of formatting each special instruction wherein said address for a resulting operand designates an address for a resulting operand currently stored in said output register.

Claim 14

The method of executing regular and special instructions of claim 11 further comprising the step of preventing activity in response to an executing special instruction in said instruction register when a resulting operand resulting from a next previous executing special instruction is not stored in said output register.

Claim 15

The method of executing regular and special instructions of claim 12 further comprising the step of resuming said activity in response to said executing special instruction in said instruction register when said resulting operand resulting from said next previous executing special instruction is stored in said output register.

Claim 16

The method of executing regular and special instructions of claim 13 further comprising the step selected from the group of steps consisting of performing integer multiplication operations, performing integer division operations, performing floating point operations, and performing double precision operations in said coprocessor unit, each of said steps performed in response to an operation code of each special instruction.

Claim 17

A pipelined central processing unit wherein execution of each instruction is partitioned into a plurality of operations, each operation capable of being completed within a predetermined time interval, said central processing unit comprising: an instruction memory unit; `an instruction register for distributing signals from an executing instruction, said executing instruction being transferred from said instruction memory unit; an operand memory unit; at least one operand register coupled to said operand memory unit for receiving operands from said operand memory unit in response to initial operand address signals in said executing instruction; an arithmetic logic unit coupled to said instruction register and said operand register for performing processing operations on initial operands stored in said operand register in response to operation code signals from said executing instruction in said instruction register, said processing operations by said arithmetic unit capable of being completed within said predetermined time interval; a first set of instructions controlling processing operations in said arithmetic unit, each of said first set of instructions having operation code signals and initial operand and resulting operand address signals, said resulting operand address signals being an address in said operand memory unit into which an operand processed by said arithmetic logic unit in response to said executing instruction in said instruction register is stored; a coprocessor unit coupled to said instruction register and to said operand register for performing processing operations on initial operands stored in said operand register not capable of being completed within said predetermined time interval, said processing operations performed in response to said operation code signals of said executing instruction in said instruction register; and a second set of instructions controlling processing operations of said coprocessor unit, each of said second set of instructions having operation code signals and initial and resulting operand address signals, wherein said second set instructions resulting operand address signals identify a location in said operand memory unit into which an initial operand processed by said coprocessor unit as a result of a processing operation determined by an operation code of a previous executing instruction in said instruction register is to be stored.

Claim 18

A pipelined central processing unit wherein execution of each instruction is partitioned into a plurality of operations, each operation capable of being completed within a predetermined time interval, said central processing unit comprising: an instruction memory unit; `an instruction register for distributing signals from an executing instruction, said executing instruction being transferred from said instruction memory unit; an operand memory unit; at least one operand register coupled to said operand memory unit for receiving operands from said operand memory unit in response to initial operand address signals in said executing instruction; an arithmetic logic unit coupled to said instruction register and said operand register for performing processing operations on initial operands stored in said operand register in response to operation code signals from said executing instruction in said instruction register, said processing operations by said arithmetic unit capable of being completed within said predetermined time interval; a first set of instructions controlling processing operations in said arithmetic unit, each of said first set of instructions having operation code signals and initial operand and resulting operand address signals, said resulting operand address signals being an address in said operand memory unit into which an operand processed by said arithmetic logic unit in response to said executing instruction in said instruction register is stored; a coprocessor unit coupled to said instruction register and to said operand register for performing processing operations on initial operands stored in said operand register not capable of being completed within said predetermined time interval, said processing operations performed in response to said operation code signals of said executing instruction in said instruction register; and a second set of instructions controlling processing operations of said coprocessor unit, each of said second set of instructions having operation code signals and initial and resulting operand address signals, wherein said second set instructions resulting operand address signals identify a location in said operand memory unit into which an initial operand processed by said coprocessor unit as a result of a processing operation determined by an operation code of a previous executing instruction in said instruction register is to be stored.

Claim 19

The pipelined central processing unit of claim 15 wherein said arithmetic logic unit can process a first set executing instruction in said instruction register while said coprocessor unit is processing a second set executing instruction previously stored in said instruction register.

Claim 20

The pipelined central processing unit of claim 16 wherein said coprocessor unit includes an output register, said pipelined central processing unit further comprising a signal means for providing a signal when a resulting operand is stored in said output register, said processing of a second set executing instruction in said instruction register being suspended when a resulting operand from a next previous second set instruction has not been stored in said output register.

Claim 21

The pipelined central processing unit of claim 17 wherein operation codes of said second set instructions designate a processing operation for said coprocessor unit selected from the group consisting of an integer division operation, an integer multiplication operation, a floating point operation, and a double precision operation.

Claim 22

The pipelined central processing unit of claim 17 wherein second set instruction processing suspended when said resulting operand is not stored in said output register is resumed when a resulting operand is stored in said output register.

Claim 23

The pipelined central processing unit of claim 15 wherein said second set instruction address signals can identify locations in said operand memory unit for two initial operands.

Claim 24

The pipelined central processing unit of claim 15 wherein said second set of instructions include at least one special instruction, said special instruction transferring an initial operand to said coprocessor unit, said initial operand being stored in two locations of said operand memory unit.