Programmable sequence controller with an arithmetic operation function

Claim 1

A programmable sequence controller comprising in combination: a sequence program memory for storing a sequence control program composed of a plurality of sequence instructions, each of said sequence instructions including any one of a test command; an output command and an arithmetic operation command in addition to address data; a program counter for selectively designating memory addresses of said sequence program memory so as to successively read out therefrom said sequence instructions; input and output selecting means responsive to address data included in any sequence instruction read out from said sequence program memory for selectively designating a plurality of input and output elements; logic operation processing means connected to said program counter for controlling the content of said program counter and also connected to said input and output selecting means and said sequence program memory for writing the operational status signal of any input element, designated by said input and output selecting means, into a test flag provided therein under a test condition designated by said test command supplied from said sequence program memory, said logic operation processing means being adapted to selectively output energization and deenergization signals based upon the status of said test flag when receiving said output command from said sequence program memory; output drive means connected to said output elements, said input and output selecting means and said logic operation processing means for energizing or deenergizing any output element, designated by said input and output selecting means, in response to said energization and deenergization signals; interrupting means included in said logic operation processing means for outputting a first interrupt signal when said logic operation processing means receives said arithmetic operation command from said sequence program memory; arithmetic operation processing means including data storage means for receiving digital data from external devices and responsive to said interrupt signal for arithmetically processing said digital data; wherein said logic operation processing means comprises: a microprogram memory for storing a plurality of microprogram instructions; an inverter for inverting said operational status signal of said any selected input elements; a data selector responsive to one of said microprogram instructions read out from said microprogram memory for selectively outputting said operational status signal and the inverted signal thereof respectively as first and second status signals; and a microprogram control unit including said test flag therein and connected to said sequence program memory and said microprogram memory for applying memory address data to said microprogram memory upon each occurrence of receiving a first part of any sequence instruction and a first part of any microprogram instruction read out respectively from said sequence program memory and said microprogram memory, said microprogram control unit being connected to said data selector and said output drive means for writing one of said first and second status signals applied from said data selector into said test flag when receiving a second part of said one of said microprogram instructions and for selectively outputting said energization and deenergization signals to said output drive means in dependence upon the status of said test flag when receiving said second part of another microprogram instruction.