Patent US4935376A successfully refreshed from Google Patents.
US4935376A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Making silicide gate level runners
Assignee: Agere Systems LLC
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Filing: 1989-10-12
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Granted: 1990-06-19
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Expires: 2009-10-12
Abstract
Abstract Integrated circuits are fabricated with thick self-aligned silicide runners on the field oxide by etching back the first dielectric to expose patterned polysilicon on the field oxide and then forming a silicide on the patterned polysilicon.
Inventors
- 👤 Steven J. Hillenius
- 👤 Kuo-Hua Lee
- 👤 Chih-Yuan Lu
- 👤 Janmye Sung
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 07:07
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/064; H10W20/066; H10D; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01304; H10D64/01306; H10D64/01308; H10D64/0131; H10D64/01326
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
88 words
A method of fabricating integrated circuits comprising the steps of: depositing a layer of a conducting gate material on a substrate which includes field oxide regions and device regions comprising a gate structure; patterning said conducting gate material on said field oxide regions; forming a first dielectric over said substrate which covers gate material; etching back said dielectric to expose the top surfaces of said conducting gate material on said field oxide regions but not said device regions; and increasing the conductivity of said exposed conducting gate material.
Claim 2
Independent Claim
88 words
A method of fabricating integrated circuits comprising the steps of: depositing a layer of a conducting gate material on a substrate which includes field oxide regions and device regions comprising a gate structure; patterning said conducting gate material on said field oxide regions; forming a first dielectric over said substrate which covers gate material; etching back said dielectric to expose the top surfaces of said conducting gate material on said field oxide regions but not said device regions; and increasing the conductivity of said exposed conducting gate material.
Claim 3
Dependent Claim
15 words
A method as recited in claim 1 in which said conducting gate material comprises polysilicon.
Claim 4
Dependent Claim
28 words
A method as recited in claim 2 in which said increasing step comprises the steps of: depositing a silicide forming transition metal; and, heating to form a silicide.
Claim 5
Dependent Claim
29 words
A method as recited in claim 1 comprising the further step of depositing and patterning a second dielectric to form windows which expose seclected portions of said device regions.
Claim 6
Dependent Claim
18 words
A method as recited in claim 4 comprising the further step of depositing a metal in said windows.
Claim 7
Dependent Claim
21 words
A method as recited in claim 1 which said increasing step comprises depositing tungsten selectively on said exposed conducting gate material.
Claim 8
Dependent Claim
18 words
A method as recited in claim 2 comprising the further step of salicidizing said source and drain regions.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-06-18 | 1993-12-18 | 1994-06-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-06-18 | 1997-12-18 | 1998-06-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-06-18 | 2001-12-18 | 2002-06-19 | $7700.00 | Window Closed / Lapsed |