← Back to Patent Explorer
JPS58130554A Expired / Lapsed JP ⏱️ 0.0 years remaining

Manufacture of semiconductor device

Assignee: Toshiba Corp
•
Filing: 1982-01-28
•
Granted: —
•
Expires: 2002-01-28
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract PURPOSE:To provide a low resistance part or a high resistance part to the titled device, by providing an energy beam reflecting mask on a poly Si pattern, irradiating the beam, and activating ion implanted impurities. CONSTITUTION:An FET is formed by a conventional method. By a high resistance poly Si layer 12, a poly Si gate 61 and a poly Si wiring 62 on a field oxide film 3 are connected. Then, an Al mask 21 is provided, P ions are implanted in the layer 12, the entire surface is irradiated by a laser beam, and the P ions are activated. The laser beam is reflected by the Al, and the implanted part of P is selectively heated. The gate electrode 61 and a high resistance layer 221 are not heated at all. Therefore, the low resistance part is not formed by the infiltration of P into the electrode 61 and the layer 221, and a wiring 22 having load resistance 221 as designed and a low resistance part 222 for a VDD wire is obtained. It is effective when P, As, and B are used for obtaining the low resistance and N, O, and Ar are used for obtaining the high resistance.

Inventors

  • 👤 Makoto Nakase
  • 👤 中瀬 真
  • 👤 Toshinobu Yanase
  • 👤 柳瀬 年延

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-01 12:54
CPC Classifications
H; H10; H10D; H10D88/00

Claims Analysis

Total Claims: 0
No claims parsed yet. Click Sync Now above to re-index claims from Google Patents.

References Cited (Backward Citations)

JPS54128689A Cited
JPS56144532A Cited
JPS56157023A Cited

USPTO Annuity & Maintenance Windows

Maintenance schedule is calculated for granted US utility patents.

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag