Method for manufacturing semiconductor devices having twin wells

Claim 1

A method for manufacturing twin well type semiconductor devices having a P-type well and an N-type well comprising the steps of: forming an insulating layer of a laminated structure having two or more layers on a semiconductor substrate of a first conductivity type; selectively removing part of said insulating layer to expose a predetermined portion of a surface of said semiconductor substrate; ion-implanting an impurity of a second conductivity type using said insulating layer as a mask to introduce the impurity of the second conductivity type into the surface of said semiconductor substrate under said insulating layer, thereby forming a first impurity region of the second conductivity type, and into that portion of said semiconductor substrate that is deeper than the surface of said semiconductor substrate and is below said predetermined portion of the substrate surface, thereby forming a second impurity region of the second conductivity type having an impurity concentration higher than that of said first impurity region; ion-implanting an impurity of the first conductivity type to introduce the impurity of the first conductivity type into said predetermined portion, thereby forming a third impurity region of the first conductivity type; removing said insulating layer; and diffusing the introduced first and second impurities by heat treatment to form a first well region of the second conductivity type in the substrate surface under a portion where said insulating layer had been formed, a second well region of the first conductivity type in the predetermined portion of the substrate surface, and an embedded region of the second conductivity type in a lower portion of the predetermined portion, said embedded region having an impurity concentration higher than that of said first well region.

Claim 2

A method for manufacturing twin well type semiconductor devices having a P-type well and an N-type well comprising the steps of: forming an insulating layer of a laminated structure having two or more layers on a semiconductor substrate of a first conductivity type; selectively removing part of said insulating layer to expose a predetermined portion of a surface of said semiconductor substrate; ion-implanting an impurity of a second conductivity type using said insulating layer as a mask to introduce the impurity of the second conductivity type into the surface of said semiconductor substrate under said insulating layer, thereby forming a first impurity region of the second conductivity type, and into that portion of said semiconductor substrate that is deeper than the surface of said semiconductor substrate and is below said predetermined portion of the substrate surface, thereby forming a second impurity region of the second conductivity type having an impurity concentration higher than that of said first impurity region; ion-implanting an impurity of the first conductivity type to introduce the impurity of the first conductivity type into said predetermined portion, thereby forming a third impurity region of the first conductivity type; removing said insulating layer; and diffusing the introduced first and second impurities by heat treatment to form a first well region of the second conductivity type in the substrate surface under a portion where said insulating layer had been formed, a second well region of the first conductivity type in the predetermined portion of the substrate surface, and an embedded region of the second conductivity type in a lower portion of the predetermined portion, said embedded region having an impurity concentration higher than that of said first well region.

Claim 13

A method for manufacturing twin well type semiconductor devices having a P-type well and an N-type well comprising the steps of: forming an insulating layer of a laminated structure including a nitride film on a P-type semiconductor substrate; selectively removing part of said insulating layer to expose a predetermined portion of a surface of said semiconductor substrate; ion-implanting phosphorus by applying an acceleration voltage of 1.5 to 2.5 MeV, using said insulating layer as a mask, to introduce phosphorus into said substrate surface under said insulating layer, thereby forming a first phosphorus region, and into a deeper portion of the predetermined portion, thereby forming a second phosphorus region having an impurity concentration higher than that of the first phosphorus region; ion-implanting boron by applying an acceleration voltage of 100 to 120 KeV, using said insulating layer as a mask, to introduce boron into said substrate surface in said predetermined portion, thereby forming a boron region; removing said insulating layer; and diffusing the introduced phosphorus and boron by heat treatment to form an N-type first well region in the substrate under a portion where said insulating layer had been formed, a P-type second well region in the predetermined portion of the substrate surface, and an N-type embedded region in a deeper portion of the predetermined portion, said embedded region having an impurity concentration higher than that of said first well region.

Claim 14

A method for manufacturing twin well type semiconductor devices having a P-type well and an N-type well comprising the steps of: forming an insulating layer of a laminated structure including a nitride film on a P-type semiconductor substrate; selectively removing part of said insulating layer to expose a predetermined portion of a surface of said semiconductor substrate; ion-implanting phosphorus by applying an acceleration voltage of 1.5 to 2.5 MeV, using said insulating layer as a mask, to introduce phosphorus into said substrate surface under said insulating layer, thereby forming a first phosphorus region, and into a deeper portion of the predetermined portion, thereby forming a second phosphorus region having an impurity concentration higher than that of the first phosphorus region; ion-implanting boron by applying an acceleration voltage of 100 to 120 KeV, using said insulating layer as a mask, to introduce boron into said substrate surface in said predetermined portion, thereby forming a boron region; removing said insulating layer; and diffusing the introduced phosphorus and boron by heat treatment to form an N-type first well region in the substrate under a portion where said insulating layer had been formed, a P-type second well region in the predetermined portion of the substrate surface, and an N-type embedded region in a deeper portion of the predetermined portion, said embedded region having an impurity concentration higher than that of said first well region.

Claim 15

A method for manufacturing twin well type semiconductor devices having a plurality of P-type well regions arranged on the surface of a P-type semiconductor substrate, a plurality of N-type well regions each of which is arranged between said P-type well regions in the semiconductor substrate, and an N-type embedded region with a high impurity concentration formed under said P-type well regions in the P-type semiconductor substrate, comprising the steps of: forming an insulating layer of a laminated structure including a nitride film on a P-type semiconductor substrate; selectively removing part of said insulating layer to expose a portion of the surface of said semiconductor substrate where a P-type well region is to be formed; ion-implanting phosphorus by applying an acceleration voltage of 1.5 to 2.5 MeV, using said insulating layer as a mask, to introduce phosphorus into said substrate surface under said insulating layer, thereby forming a first phosphorus region, and into a lower portion of the predetermined portion, thereby forming a second phosphorus region having an impurity concentration higher than that of said first phosphorus region; ion-implanting boron by applying an acceleration voltage of 100 to 120 KeV, using said insulating layer as a mask, to introduce boron into the portion of the substrate where the P-type well region is to be formed, thereby forming a boron region; removing said insulating layer; and effecting heat treatment to diffuse the introduced phosphorus and boron.

Claim 16

A method for manufacturing twin well type semiconductor devices having a plurality of P-type well regions arranged on the surface of a P-type semiconductor substrate, a plurality of N-type well regions each of which is arranged between said P-type well regions in the semiconductor substrate, and an N-type embedded region with a high impurity concentration formed under said P-type well regions in the P-type semiconductor substrate, comprising the steps of: forming an insulating layer of a laminated structure including a nitride film on a P-type semiconductor substrate; selectively removing part of said insulating layer to expose a portion of the surface of said semiconductor substrate where a P-type well region is to be formed; ion-implanting phosphorus by applying an acceleration voltage of 1.5 to 2.5 MeV, using said insulating layer as a mask, to introduce phosphorus into said substrate surface under said insulating layer, thereby forming a first phosphorus region, and into a lower portion of the predetermined portion, thereby forming a second phosphorus region having an impurity concentration higher than that of said first phosphorus region; ion-implanting boron by applying an acceleration voltage of 100 to 120 KeV, using said insulating layer as a mask, to introduce boron into the portion of the substrate where the P-type well region is to be formed, thereby forming a boron region; removing said insulating layer; and effecting heat treatment to diffuse the introduced phosphorus and boron.