Digital phase lock loop

Claim 1

A method for generating a digital clock signal which is frequency and phase referenced to an external digital data signal, the phase of said digital data signal initialized to a phase lock point arbitrarily determined, the slope of said digital clock signal initialized to a desired initial slope value, said external digital data signal subject ot variations in data frequency and high frequency jitter unrelated to changes in said data frequency, said method comprising the steps of: for each clock cycle of said digital clock signal; adding the value of slope of the clock signal to the value of phase of the digital data signal to obtain an uncompensated value of phase, generating a clock pulse when said uncompensated value of phase is greater than or equal to a predetermined value, and reinitializing the value of phase by subtracting said predetermined value from said value of phase, minitoring said external digital data signal for a pulse of said external digital data; operative when said pulse of external digital data is detected, subtracting said phase lock point from the value of phase to determine phase error, filtering said phase error to generate a phase correction value, adding said phase correction value to said uncompensated phase value to obtain a compensated phase value, determining the difference between the phase error for the current clock cycle and the previous clock cycle to obtain an uncompensated value of slope error, filtering said slope error to generate a slope correction value, adding the slope correction value to the slope to obtain a compensated slope value, and adding the compensated slope value to the compensated phase value to obtain a new phase value, said new phase value being the starting phase value of the next clock cycle, whereby the phase and/or slope are compensated in order to generate a digital clock signal which closely references said external digital data signal.

Claim 2

A method for generating a digital clock signal which is frequency and phase referenced to an external digital data signal, the phase of said digital data signal initialized to a phase lock point arbitrarily determined, the slope of said digital clock signal initialized to a desired initial slope value, said external digital data signal subject ot variations in data frequency and high frequency jitter unrelated to changes in said data frequency, said method comprising the steps of: for each clock cycle of said digital clock signal; adding the value of slope of the clock signal to the value of phase of the digital data signal to obtain an uncompensated value of phase, generating a clock pulse when said uncompensated value of phase is greater than or equal to a predetermined value, and reinitializing the value of phase by subtracting said predetermined value from said value of phase, minitoring said external digital data signal for a pulse of said external digital data; operative when said pulse of external digital data is detected, subtracting said phase lock point from the value of phase to determine phase error, filtering said phase error to generate a phase correction value, adding said phase correction value to said uncompensated phase value to obtain a compensated phase value, determining the difference between the phase error for the current clock cycle and the previous clock cycle to obtain an uncompensated value of slope error, filtering said slope error to generate a slope correction value, adding the slope correction value to the slope to obtain a compensated slope value, and adding the compensated slope value to the compensated phase value to obtain a new phase value, said new phase value being the starting phase value of the next clock cycle, whereby the phase and/or slope are compensated in order to generate a digital clock signal which closely references said external digital data signal.

Claim 9

A apparatus for generating a digital clock signal which is frequency and phase referenced to an external digital data signal, the phase of said digital data signal initialized to a phase lock point arbitrarily determined, the slope of said digital clock signal initialized to a desired initial slope value, said external digital data signal subject to variations in data frequency and high frequency jitter unrelated to changes in said data frequency, said apparatus comprising: means for adding the value of slope of the clock signal to the value of phase of the digital data signal to obtain an uncompensated value of phase, means for generating a clock pulse when said uncompensated value of phase is greater than or equal to a predetermined value, and means for reinitializing the value of phase by subtracting said predetermined value from said value of phase means form monitoring said external digital data signal for a pulse of said external digital data; means for subtracting said phase lock point from said value of phase to determine phase error, means for filtering said phase error to generate a phase correction value, means for adding said phase correction value to said uncompensated phase value to obtain a compensated phase value, means for determining the difference between the phase error for the current clock cycle and the previous clock cycle to obtain an uncompensated value of slope error, means for filtering said slope error to generate a slope correction value, means for adding the slope correction value to the slope to obtain a compensated slope value, and means for adding the compensated slope value to the compensated phase value to obtain a new phase value, said new phase value being the starting phase value of the next clock cycle, whereby the phase and/or slope are compensated in order to generate a digital clock signal which closely references said external digital data signal.

Claim 10

A apparatus for generating a digital clock signal which is frequency and phase referenced to an external digital data signal, the phase of said digital data signal initialized to a phase lock point arbitrarily determined, the slope of said digital clock signal initialized to a desired initial slope value, said external digital data signal subject to variations in data frequency and high frequency jitter unrelated to changes in said data frequency, said apparatus comprising: means for adding the value of slope of the clock signal to the value of phase of the digital data signal to obtain an uncompensated value of phase, means for generating a clock pulse when said uncompensated value of phase is greater than or equal to a predetermined value, and means for reinitializing the value of phase by subtracting said predetermined value from said value of phase means form monitoring said external digital data signal for a pulse of said external digital data; means for subtracting said phase lock point from said value of phase to determine phase error, means for filtering said phase error to generate a phase correction value, means for adding said phase correction value to said uncompensated phase value to obtain a compensated phase value, means for determining the difference between the phase error for the current clock cycle and the previous clock cycle to obtain an uncompensated value of slope error, means for filtering said slope error to generate a slope correction value, means for adding the slope correction value to the slope to obtain a compensated slope value, and means for adding the compensated slope value to the compensated phase value to obtain a new phase value, said new phase value being the starting phase value of the next clock cycle, whereby the phase and/or slope are compensated in order to generate a digital clock signal which closely references said external digital data signal.