High order digital phase lock loop system

Claim 2

A digital phase lock loop system for providing a digital output signal synchronized with a stream of data pulses having a nominal data frequency, said stream of data pulses being subject to low frequency variations in the data frequency and high frequency variations unrelated to changes in the data frequency, said system comprising: variable oscillator means for generating a digital output signal comprised of a plurality of pulse windows in which each window is defined by a plurality of successive states of equal duration; and processing means for controlling the number of states in each window as a function of the phase difference between the output signal and the stream of data pulses, said processing means including means for filtering phase differences resulting from said high frequency variations in the stream of data pulses thereby to accurately track said low frequency variations.

Claim 3

The system of claim 1 wherein the processing means comprises means for determining the phase of each data pulse with respect to a window in which it occurs, means for controlling the number of states in each window as a function of the determined phase for the data pulse occurring in that window and means for controlling the number of states in each window as a function of the determined phase for the data pulse occurring in that window and the determined phase for a data pulse occurring in at least one previous window.

Claim 4

The system of claim 2 wherein: the phase of each data pulse is determined by determining the state of a window in which the data pulse occurs; each state of a window has an instantaneous correction weight associated with it, wherein the total number of states in the window is altered in correspondence with the correction weight of the state in which the data pulse occurs; and various states of each window are separated into increase regions and decrease regions, wherein the total number of states in the window is increased if data pulses occur in the increase region in successive windows and the number of states in the window is decreased if data pulses occur in the decrease region in successive windows.

Claim 5

The system of claim 3 wherein the number of states in each window, and therefore the frequency of the window pulses, is set prior to the generation of each window and wherein: alterations in accordance with the instantaneous correction weights are accomplished on a window-by-window basis; and alterations in accordance with the occurrence of successive pulses in the increase or decrease regions are accomplished to alter the set number of states, and therefore frequency, for subsequent window pulses.

Claim 6

The system of claim 1, 2, 3 or 4 wherein the variable oscillator means comprises a variable length shift register.

Claim 7

The system of claim 1, 2, 3, 4 or 5 wherein the processing means comprises a programmed logic array.

Claim 8

A digital phase lock loop system for providing a clock signal of successive windows of high and low values which is phase and frequency referred to an external data pulse input signal having a nominal data frequency, wherein said input signal is subject to low frequency variations about the nominal frequency and random high frequency variations, the system comprising: a sample clock; a variable length multiple state ring shift register, driven by the sample clock, wherein each window of the system clock signal is defined by the number of states in the shift register; and processing means for controlling the number of states in the shift register to thereby control the frequency of the system clock signal, said processing means including: means for determining for each window the shift register state in which an external data pulse arrives to thereby determine the phase of the data pulses with respect to the windows; means for setting the number of states, and therefore the clock frequency, in each window prior to the generation of the window; means for correcting the state setting for subsequent windows as a function of the determination of the state of arrival of a data pulse, including means for filtering the high frequency variations of the data pulses to minimize their effect on correction of state settings for subsequent windows.

Claim 9

A digital phase lock loop system for providing a clock signal of successive windows of high and low values which is phase and frequency referred to an external data pulse input signal having a nominal data frequency, wherein said input signal is subject to low frequency variations about the nominal frequency and random high frequency variations, the system comprising: a sample clock; a variable length multiple state ring shift register, driven by the sample clock, wherein each window of the system clock signal is defined by the number of states in the shift register; and processing means for controlling the number of states in the shift register to thereby control the frequency of the system clock signal, said processing means including: means for determining for each window the shift register state in which an external data pulse arrives to thereby determine the phase of the data pulses with respect to the windows; means for setting the number of states, and therefore the clock frequency, in each window prior to the generation of the window; means for correcting the state setting for subsequent windows as a function of the determination of the state of arrival of a data pulse, including means for filtering the high frequency variations of the data pulses to minimize their effect on correction of state settings for subsequent windows.

Claim 10

The system of claim 7 wherein: plural states in each window to one side of a reference state are in an increase region and plural states to the other side of the reference state are in a decrease region, wherein the means for correcting increases the state setting when data pulses arrive in increase regions in consecutive windows and decreases the state setting when data pulses arrive in decrease regions in consecutive windows.

Claim 11

The system of claim 8 wherein each state of each window has an instantaneous correction weight associated with it, wherein the means for filtering includes means for altering the number of states in a window in accordance with the correction weight of the state in which a data pulse occurred in that window, wherein said altering has no effect on the state setting for subsequent windows.

Claim 12

The system of claim 9 wherein said correction weights are greatest in magnitude at the edges of each window and least in magnitude near the center of each window.

Claim 13

The system of claim 7,8,9 or 10 wherein the processing means comprises a programmed logic array.

Claim 14

In a data separator for separating clock from data transition pulses in MFM encloded signals having a nominal data rate and being subject to high frequency variations unrelated to the nominal data rate, a digital phase lock loop system for generating a recovered clock signal in response to the reading of the transition pulses, comprising: a sample clock having a frequency which is a multiple of a nominal frequency of the MFM signal; a variable multiple state counting means driven by the sample clock and providing an output signal to toggle the recovered clock signal after a window comprised of some number of sample clock pulses as defined by the number of states of the counting means; processing means for controlling the number of states in each window as a function of a determination of the state of occurrence of transistion pulses in the windows, said processing means including means for filtering the effects of variations in the locations of transition pulses in the windows caused by high frequency variations, said processing thereby causing the recovered clock signal to accurately track low frequency variations in the MFM encoded signals about the nominal data rate.

Claim 15

In a data separator for separating clock from data transition pulses in MFM encloded signals having a nominal data rate and being subject to high frequency variations unrelated to the nominal data rate, a digital phase lock loop system for generating a recovered clock signal in response to the reading of the transition pulses, comprising: a sample clock having a frequency which is a multiple of a nominal frequency of the MFM signal; a variable multiple state counting means driven by the sample clock and providing an output signal to toggle the recovered clock signal after a window comprised of some number of sample clock pulses as defined by the number of states of the counting means; processing means for controlling the number of states in each window as a function of a determination of the state of occurrence of transistion pulses in the windows, said processing means including means for filtering the effects of variations in the locations of transition pulses in the windows caused by high frequency variations, said processing thereby causing the recovered clock signal to accurately track low frequency variations in the MFM encoded signals about the nominal data rate.

Claim 16

The system of claim 12 wherein each window has a reference state and a plurality of states in an increase region to one side of the reference state and a plurality of states in a decrease region to the other side of the reference state, and wherein each state in a window has an instantaneous correction weight associated with it, wherein the processing means comprises means for: setting the number of states per window prior to the generation of each window in accordance with a desired recovered clock frequency; determining if transition pulses occur in either successive increase regions or successive decrease regions and, if so, altering the set number of states per window in accordance with a new desired frequency; altering the number of states in each window in accordance with the correction weight associated with the state of occurrence of a transition pulse in that window.

Claim 17

The system of claim 13 wherin the correction weight is zero for the reference state and increases to a maximum at each edge of every window.