Abstract A reference source of digital pulses of a first frequency f 1 is coupled to the input of a frequency synthesizer which is capable of providing a second frequency f 2 output signal. The second frequency is related to the first frequency by a predetermined, rational fraction (e.g., as f 2 = (M/N)f 1 ). The synthesizer includes a phase control unit comprising an adder by way of which a first number N is added each sample period to a remainder, the sum output of the adder being operated upon modulo a second number M, e.g., by dividing by M and discarding a resultant quotient to obtain a remainder. The remainder, having a value between zero and M-1, is compared to a prefixed signal, illustratively the largest integer in M/2. If the remainder is less than the prefixed signal, a first logic state control signal is provided to a control system; else a second logic state signal is so provided. The alternation between the first and second logic states is such that M pulses of the second frequency occur for every N pulses of the first frequency. Thereby, the second frequency is synthesized responsive to the first.
A frequency synthesizer including a first terminal adapted for receiving a first frequency signal, first means responsive to said first frequency signal for extending a synthesized second frequency signal to an output terminal; said first extending means including a control unit responsive to one of said frequency signals for providing a control signal said control unit including an accumulator, said accumulator including apparatus for adding a first number to an output of said accumulator to obtain a sum, and said first extending means including a control system responsive to said control signal and to the other one of said frequency signals for controlling said second frequency signal and CHARACTERIZED IN THAT said synthesizer comprises: means for providing a modulo remainder of said sum, said remainder being provided modulo a second number, second means responsive to said one of said frequency signals for extending said remainder to said output of said accumulator, means for comparing said extended remainder to a prefixed signal, said prefixed signal being equal to the value of a function of said second number, and third means responsive to said comparing means for extending said control signal to said control system.
Claim 2
Dependent Claim
193 words
A frequency synthesizer including a first terminal adapted for receiving a first frequency signal, first means responsive to said first frequency signal for extending a synthesized second frequency signal to an output terminal; said first extending means including a control unit responsive to one of said frequency signals for providing a control signal said control unit including an accumulator, said accumulator including apparatus for adding a first number to an output of said accumulator to obtain a sum, and said first extending means including a control system responsive to said control signal and to the other one of said frequency signals for controlling said second frequency signal and CHARACTERIZED IN THAT said synthesizer comprises: means for providing a modulo remainder of said sum, said remainder being provided modulo a second number, second means responsive to said one of said frequency signals for extending said remainder to said output of said accumulator, means for comparing said extended remainder to a prefixed signal, said prefixed signal being equal to the value of a function of said second number, and third means responsive to said comparing means for extending said control signal to said control system.
Claim 3
Dependent Claim
29 words
The apparatus defined in claim 1 wherein said second frequency signal is related to said first frequency signal according to a ratio of said first and said second numbers.
Claim 4
Dependent Claim
15 words
The apparatus defined in claim 2 wherein said ratio may be a predetermined rational fraction.
Claim 5
Dependent Claim
38 words
The apparatus defined in claim 1 wherein said remainder comparison means includes apparatus for comparing said remainder to said prefixed signal, said prefixed signal being equal to the largest integer within the value of one-half said second number.