Patent US4928223A successfully refreshed from Google Patents.
US4928223A
Expired / Lapsed
US
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Floating point microprocessor with directable two level microinstructions
Assignee: National Semiconductor Corp
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Filing: 1986-08-28
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Granted: 1990-05-22
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Expires: 2006-08-28
Abstract
Abstract A microprocessor integrator circuit includes split nanocode memories which enables simultaneous execution of an arithmetic operation and an operand fetch for maximizing through-put. The circuit also includes a shared sequencing arithmetic logic unit which handles all microcode sequencing plus memory address sequencing. The circuit also provides nanocode sequencing which enables storage of constants and data in a microcode space which can include an off-chip writable control store. In addition, two level microcode is utilized to enable long routines to be vertically encoded without the overhead of a large number of read only memory outputs.
Inventors
- 👤 Tich T. Dao
- 👤 Gary R. Burke
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 08:07
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/22; G06F9/26; G06F7/00; G06F7/38; G06F7/48; G06F7/483; G06F9/30; G06F9/38; G06F9/3885; G06F9/3889
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
214 words
A microprocessor comprising: (a) an instruction sequence register having an instruction address and connected to provide said instruction address to means for storing a first level of instruction; (b) a first level instruction register connected to receive a first level instruction from said first level instruction storage means; (c) means for storing a second level of instructions connected to receive an address from said first level instruction register, said second level instruction storage means comprising: (i) first means for storing a first portion of said second level instruction; and (ii) separate second means for storing a second portion of said second level instructions, (d) a first, second level instruction register connected to receive said first portion of said second level instruction; and, (e) a second, second level instruction register connected to receive said second portion of said second level instructions, wherein said first and second, second level instruction registers are connected to supply instruction portions to said first means for storing a first portion of said second level instructions and said separate second means for storing a second portion of said second level instructions respectively and at least a portion of instructions output from said first, second level instruction register is coupled to an input of said instruction sequence register through branch control means.
Claim 2
Dependent Claim
214 words
A microprocessor comprising: (a) an instruction sequence register having an instruction address and connected to provide said instruction address to means for storing a first level of instruction; (b) a first level instruction register connected to receive a first level instruction from said first level instruction storage means; (c) means for storing a second level of instructions connected to receive an address from said first level instruction register, said second level instruction storage means comprising: (i) first means for storing a first portion of said second level instruction; and (ii) separate second means for storing a second portion of said second level instructions, (d) a first, second level instruction register connected to receive said first portion of said second level instruction; and, (e) a second, second level instruction register connected to receive said second portion of said second level instructions, wherein said first and second, second level instruction registers are connected to supply instruction portions to said first means for storing a first portion of said second level instructions and said separate second means for storing a second portion of said second level instructions respectively and at least a portion of instructions output from said first, second level instruction register is coupled to an input of said instruction sequence register through branch control means.
Claim 3
Dependent Claim
24 words
A microprocessor in accordance with claim 1 wherein said first level instruction register is connected to provide an address to said instruction sequence register.
Claim 4
Dependent Claim
42 words
A microprocessor in accordance with claim 1 wherein at least a portion of instructions output from said first, second level instruction register is coupled to a control input of at least one arithmetic logic unit for controlling data movement in said microprocessor.
Claim 5
Dependent Claim
50 words
A microprocessor in accordance with claim 3 wherein at least a portion of instruction output from said second, second level instruction register is coupled to an input of said instruction sequence register for controlling first level address sequencing and operation of said means for storing a first level of instructions.
Claim 6
Dependent Claim
26 words
A microprocessor in accordance with claim 4 wherein said first means for storing a first poriton of said second level instructions comprises a read only memory.
Claim 7
Dependent Claim
26 words
A microprocessor in accordance with claim 5 wherein said second means for storing a second portion of said second level instructions comprises a programmable logic array.
Claim 8
Dependent Claim
32 words
A microprocessor in accordance with claim 4 additionally comprising means for connecting, in parallel with said means for storing a first level of instructions, external means for storing additional first level instructions.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-05-21 | 1993-11-20 | 1994-05-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-05-21 | 1997-11-20 | 1998-05-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-05-21 | 2001-11-20 | 2002-05-22 | $7700.00 | Window Closed / Lapsed |