Integrated circuit device having a chip

Claim 1

An integrated circuit device on a chip comprising: pairs of p-channel device formation regions and n-channel device formation regions formed on the chip in arrays, each of said pairs having a p-channel device formation region and an n-channel device formation region, the p-channel device formation region having an n-type semiconductor region, p-type source and drain regions provided in the n-type semiconductor region with a space therebetween, and a p-channel gate electrode provided on a first insulating layer formed on the n-type semiconductor region between the p-type source and drain regions, the n-channel device formation region having a p-type semiconductor region, n-type source and drain regions provided in the p-type semiconductor region with a space therebetween, and an n-channel gate electrode provided on a second insulating layer formed on the p-type semiconductor region, said pairs of the p-channel device formation regions and the n-channel device formation regions form adjacent pairs, the adjacent pairs arranged with the p-channel device formation regions adjacent to one another and the n-channel device formation regions adjacent to one another; a first wiring channel provided in a surface of the chip between the n-channel device formation regions of two of the adjacent pairs; a first power source wiring layer, situated in said first wiring channel, comprising a metal layer in contact with the n-type source region and the p-type semiconductor region provided in the n-channel device formation regions positioned at either side of said first wiring channel; a third insulating layer provided in said first wiring channel on said first power source wiring layer; a second wiring channel provided in a surface of the chip between the p-channel device formation regions of two of the adjacent pairs; a second power source wiring layer, situated in said second wiring channel, comprising a metal layer in contact with the p-type source region and the n-type semiconductor region provided in the p-channel device formation regions positioned at either side of said second wiring channel; a fourth insulating layer provided in said second wiring channel on said second power source wiring layer; isolation regions formed from a fifth insulating layer provided on a surface of the chip between the p-channel device formation regions and the n-channel device formation regions of each of said pairs; and means acting as an input terminal, for connecting the gate electrodes respectively provided in the n-channel and the p-channel device formation regions positioned at either side of said isolation regions for each of said pairs.