Gate array integrated device having mixed single column type and matrix type arrays

Claim 2

A gate array integrated device comprising: a plurality of single column type arrays each including a series of basic cells arranged in columns; a plurality of matrix type arrays each including a plurality of arrays arranged in proximity to each other in rows, each of said arrays including a series of basic cells arranged in columns; a plurality of first power supply lines arranged in columns over said single column type arrays and said matrix type arrays; and longitudinal connection areas, arranged in columns between said single column type arrays and said matrix type arrays, for providing connection areas for connecting said basic cells to each other, thereby creating unit cells, each of said matrix type arrays having first and second sides, one of said single column type arrays facing at least one of said first and second sides of each of said matrix type arrays.

Claim 3

A device as set forth in claim 1, wherein each of said basic cells comprises P-channel transistors and N-channel transistors.

Claim 4

A device as set forth in claim 2, wherein adjacent ones of said arrays within one of said matrix type arrays have an "image by inversion" relationship with respect to each other regarding the arrangement of said P-channel and N-channel transistors.

Claim 5

A device as set forth in claim 1, wherein said basic cells have gates, further comprising: traverse connection areas arranged in rows between said basic cells of said single column type arrays and said matrix type arrays; impurity diffusion regions, formed on said traverse connection areas and crossing said single column type arrays, for providing a substrate bias thereto; a plurality of second power supply lines arranged on said traverse connection areas; means, operatively connected to said single column type arrays and said first and second power supply lines, for clipping one of said gates of said basic cells in said single column type arrays to one of said first and second power supply lines; and means, operatively connected to said single column type arrays and said impurity diffusion regions, for clipping one of said gates of said basic cells in said single column type arrays to one of said impurity diffusion regions formed in said traverse connection area adjacent to said basic cells when said first and second power supply lines do not have a desired potential.

Claim 6

A device as set forth in claim 4, further comprising a plurality of third power supply lines each arranged over and connected to said first power supply lines, respectively.

Claim 7

A device as set forth in claim 5, wherein said third power supply lines are wider than said first power supply lines.

Claim 8

A device as set forth in claim 1, further comprising: traverse connection areas arranged in rows between said basic cells of said single column type arrays and said matrix type arrays; impurity diffusion regions, formed on said traverse connection areas and crossing said matrix column type arrays, for providing a substrate bias thereto; a plurality of second power supply lines arranged on said traverse connection areas; means, operatively connected to said matrix type arrays and one of said first and second power supply lines, for clipping one of said gates of one of said basic cells in said matrix type arrays to one of said first and second power supply lines; and means, operatively connected to said impurity diffusion regions and said matrix type arrays, for clipping one of said gates of one of said basic cells in said matrix type arrays to one of said impurity diffusion regions formed in said traverse connection areas adjacent to said one of said gates.

Claim 9

A device as set forth in claim 7, further comprising a plurality of third power supply lines each arranged over and connected to said first power supply lines, respectively.

Claim 10

A device as set forth in claim 8, wherein said third power supply lines are wider than said first power supply lines.

Claim 11

A gate array integrated device comprising: matrix type arrays arranged in columns and including basic cells; single column type arrays arranged in columns between said matrix type arrays and including basic cells; longitudinal connection areas, arranged between said matrix type arrays and said single column type arrays for connecting said basic cells; traverse connection areas arranged between said basic cells of said matrix cell arrays and said basic cells of said single column type arrays and perpendicular to said longitudinal connection areas; first power supply lines formed on said matrix type arrays and said single column type arrays; and second power supply lines perpendicular to said first power supply lines and formed on said traverse connection areas.

Claim 12

A gate array integrated device comprising: matrix type arrays arranged in columns and including basic cells; single column type arrays arranged in columns between said matrix type arrays and including basic cells; longitudinal connection areas, arranged between said matrix type arrays and said single column type arrays for connecting said basic cells; traverse connection areas arranged between said basic cells of said matrix cell arrays and said basic cells of said single column type arrays and perpendicular to said longitudinal connection areas; first power supply lines formed on said matrix type arrays and said single column type arrays; and second power supply lines perpendicular to said first power supply lines and formed on said traverse connection areas.