US4564773A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor gate array device having an improved interconnection structure
Assignee: Fujitsu Ltd
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Filing: 1982-08-11
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Granted: 1986-01-14
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Expires: 2002-08-11
Abstract
Abstract In a semiconductor device having a gate array structure, a macro-cell includes more basic cells than conventional macro-cells, for preforming a logic function, whereby the density of the terminals in a direction vertical to a direction in which wiring lines are drawn, is decreased.
Inventors
- 👤 Tetsu Tanizawa
- 👤 Hitoshi Omichi
- 👤 Yoshiharu Mitono
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 16:39
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/17748; H03K19/1733; H03K19/1735; H03K19/17704; H03K19/17724; H03K19/17728; H03K19/17736; H10; H10D; H10D84/00; H10D84/90; H10D84/901; Y; Y10; Y10S; Y10S257/00; Y10S257/923
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
108 words
A semiconductor device having a gate array structure, wiring channels, and wiring lines, comprising: macro-cells formed on a semiconductor chip, each of said macro-cells comprising: basic cells having terminals and performing a logic function; and at least one of said macro-cells comprising more than a minimum number of said basic cells necessary to perform the logic function to be realized by said at least one of said macro-cells, thereby decreasing the ratio between the number of terminals in said at least one of said macro-cells and the number of wiring channels across said at least one of said macro-cells, on and along which the wiring lines are distributed.
Claim 2
Dependent Claim
108 words
A semiconductor device having a gate array structure, wiring channels, and wiring lines, comprising: macro-cells formed on a semiconductor chip, each of said macro-cells comprising: basic cells having terminals and performing a logic function; and at least one of said macro-cells comprising more than a minimum number of said basic cells necessary to perform the logic function to be realized by said at least one of said macro-cells, thereby decreasing the ratio between the number of terminals in said at least one of said macro-cells and the number of wiring channels across said at least one of said macro-cells, on and along which the wiring lines are distributed.
Claim 3
Dependent Claim
61 words
A logic circuit formed using a gate array structure, comprising: a macro-cell, including: basic cells operatively connected to form said macro-cell, the number of said basic cells being greater than a minimum number of said basic cells necessary to form the logic circuit realized by said macro-cell; and lateral wiring routes passing through said macro-cell over each of said basic cells.
Claim 4
Dependent Claim
61 words
A logic circuit formed using a gate array structure, comprising: a macro-cell, including: basic cells operatively connected to form said macro-cell, the number of said basic cells being greater than a minimum number of said basic cells necessary to form the logic circuit realized by said macro-cell; and lateral wiring routes passing through said macro-cell over each of said basic cells.
Claim 5
Dependent Claim
28 words
A logic circuit as set forth in claim 2, wherein there is at least one unused lateral wiring route passing through each said basic cell of said macro-cell.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-01-13 | 1989-07-15 | 1990-01-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-01-13 | 1993-07-15 | 1994-01-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-01-13 | 1997-07-15 | 1998-01-14 | $7700.00 | Window Closed / Lapsed |