Apparatus for physically locating faulty electrical components

Claim 2

Apparatus for determining the physical location of a faulty computer component, for use with a computer system having separate data, address, and control signal buses and further having addressable components mounted on a plurality of physically separate mounting boards, said apparatus comprising, means for generating an error signal when an error is detected at a specific address, means responsive to the generation of said error signal for storing the address corresponding to the location causing said error signal in first storage means, means for placing said address corresponding to the location of said error on the address bus, means associated with each mounting board for generating a board select signal when an address which is physically located on that board is placed on the address bus, means responsive to the generation of said error signal and said board select signal for storing a signal in a second storage means for indicating the faulty mounting board.

Claim 3

Apparatus according to claim 1 wherein said second storage means contains a bit location corresponding to each separate mounting board in the computer system and which has an input line for each bit location, each input line being operatively connected to the output of the board select signal of the corresponding mounting board.

Claim 4

Apparatus according to claim 1 further comprising, means for selectively disabling said board select signals such that said board select signals do not reach said second storage means.

Claim 5

Apparatus for determining the physical location of a faulty component according to claim 1 wherein said means for generating an error signal comprises an error circuit on said board.

Claim 6

Apparatus for determining the physical location of a faulty component according to claim 4 wherein said multiplexer has a pair of inputs, one from said board select signal generating means and the other from said error circuit, the output of aid multiplexer coupled to said error storing means on the board.

Claim 7

In a computer system having a central processing unit, addressable components mounted on a plurality of physically separate mounting boards and separate data, address, and control signal busses connecting all components to the CPU, an apparatus for determining the physical location of a faulty computer component comprising: a plurality of mounting boards, each board comprising: (A) a plurality of computer components, (B) a multiplexer having a plurality of inputs, a single output and control inputs, (C) board select circuitry, having inputs which are connected to the address bus and a single output, said circuitry adapted to output a first signal when the address on the address bus is physically located on that board and a second signal otherwise, (D) address parity check circuitry having inputs connected to the address bus and a single output, said circuitry adapted to output a first signal when it detects an address parity error and a second signal otherwise, (E) the output of said board select circuitry connected to one input of said multiplexer, (F) the output of said parity check circuitry connected to another input of said multiplexer; a decoder having an output associated with each mounting board and a plurality of control inputs; a diagnostic register for controlling said multiplexers and said decoder, the inputs of said diagnostic register connected to said data bus in order to receive instructions from said CPU and the outputs connected to said multiplexers control inputs and said decoder control inputs; a memory controller comprising; (A) a parity error register having a bit location associated with each mounting board and an input line and output line for each bit, (B) an AND gate associated with each mounting board in the computer system, having two inputs, (C) one of each of said AND gate inputs being connected to the output of the associated mounting board multiplexer and the other of each of said AND gate inputs being connected to the associated output of the decoder, (D) the output of each of said AND gates being connected to the associated input of the parity error register, (E) the output line for each bit of said parity error register connected to the data bus.

Claim 8

In a computer system having a central processing unit, addressable components mounted on a plurality of physically separate mounting boards and separate data, address, and control signal busses connecting all components to the CPU, an apparatus for determining the physical location of a faulty computer component comprising: a plurality of mounting boards, each board comprising: (A) a plurality of computer components, (B) a multiplexer having a plurality of inputs, a single output and control inputs, (C) board select circuitry, having inputs which are connected to the address bus and a single output, said circuitry adapted to output a first signal when the address on the address bus is physically located on that board and a second signal otherwise, (D) address parity check circuitry having inputs connected to the address bus and a single output, said circuitry adapted to output a first signal when it detects an address parity error and a second signal otherwise, (E) the output of said board select circuitry connected to one input of said multiplexer, (F) the output of said parity check circuitry connected to another input of said multiplexer; a decoder having an output associated with each mounting board and a plurality of control inputs; a diagnostic register for controlling said multiplexers and said decoder, the inputs of said diagnostic register connected to said data bus in order to receive instructions from said CPU and the outputs connected to said multiplexers control inputs and said decoder control inputs; a memory controller comprising; (A) a parity error register having a bit location associated with each mounting board and an input line and output line for each bit, (B) an AND gate associated with each mounting board in the computer system, having two inputs, (C) one of each of said AND gate inputs being connected to the output of the associated mounting board multiplexer and the other of each of said AND gate inputs being connected to the associated output of the decoder, (D) the output of each of said AND gates being connected to the associated input of the parity error register, (E) the output line for each bit of said parity error register connected to the data bus.

Claim 9

Apparatus for determining the physical location of a faulty electric component, said apparatus being for use with a computer system having components with addressable locations mounted on a plurality of physically separate mounting boards, and a means for generating address signals to select one of said plurality of locations, said apparatus comprising: means responsive to the detection of an error associated with a board for generating an error signal, means for receiving and storing said error signal, means associated with each of said mounting boards and responsive to said address signals for generating a board select signal if said address signals select a location on that board, first diagnostic control means responsive to the generation of said error signal for storing the address signals corresponding to the location causing said error signal, and second diagnostic control means responsive to the generation of said error signal and said board select signal for storing a signal representative of the faulty board, said first diagnostic control means using said stored address signals to reselect said location causing said error, said first diagnostic control means thereupon examining said signal representative of the faulty board to determine the faulty mounting board.

Claim 10

Apparatus for determining the physical location of a faulty electric component, said apparatus being for use with a computer system having components with addressable locations mounted on a plurality of physically separate mounting boards, and a means for generating address signals to select one of said plurality of locations, said apparatus comprising: means responsive to the detection of an error associated with a board for generating an error signal, means for receiving and storing said error signal, means associated with each of said mounting boards and responsive to said address signals for generating a board select signal if said address signals select a location on that board, first diagnostic control means responsive to the generation of said error signal for storing the address signals corresponding to the location causing said error signal, and second diagnostic control means responsive to the generation of said error signal and said board select signal for storing a signal representative of the faulty board, said first diagnostic control means using said stored address signals to reselect said location causing said error, said first diagnostic control means thereupon examining said signal representative of the faulty board to determine the faulty mounting board.

Claim 11

Apparatus for determining the physical location of a faulty component according to claim 7 wherein said second diagnostic control means comprises an error storing means, a control register for receiving diagnostic control information from said central processing unit and generating a diagnostic control signal, and a multiplexer responsive to said diagnostic control signal and having an input connected to said board select signal generating means and an output connected to said error signal storing means.

Claim 12

Apparatus for determining the physical location of a faulty component, said apparatus being for use with a computer system having various components mounted on a plurality of mounting boards, said computer system having a memory with a plurality of memory locations, sets of said memory locations being located on physically different mounting boards, and a means for generating address signals to select one of said plurality of memory locations, said apparatus comprising: means for generating an error signal when an error is detected, means for receiving and storing said error signal, means located on each of said mounting boards and responsive to said address signals for generating a board select signal if said address signals select a memory location on that board, first diagnostic control means responsive to the generation of an error signal for storing the address signals corresponding to the memory location causing said error signal, and second diagnostic control means responsive to the generation of said error signals and said board select signal for storing a signal representative of the faulty board, said first diagnostic control means using said stored address signals to reselect said memory location causing said error, said first diagnostic control means thereupon examining said signal representative of the faulty board to determine the faulty mounting board.

Claim 13

Apparatus for determining the physical location of a faulty component, said apparatus being for use with a computer system having various components mounted on a plurality of mounting boards, said computer system having a memory with a plurality of memory locations, sets of said memory locations being located on physically different mounting boards, and a means for generating address signals to select one of said plurality of memory locations, said apparatus comprising: means for generating an error signal when an error is detected, means for receiving and storing said error signal, means located on each of said mounting boards and responsive to said address signals for generating a board select signal if said address signals select a memory location on that board, first diagnostic control means responsive to the generation of an error signal for storing the address signals corresponding to the memory location causing said error signal, and second diagnostic control means responsive to the generation of said error signals and said board select signal for storing a signal representative of the faulty board, said first diagnostic control means using said stored address signals to reselect said memory location causing said error, said first diagnostic control means thereupon examining said signal representative of the faulty board to determine the faulty mounting board.

Claim 14

Apparatus for determining the physical location of a faulty memory component according to claim 9 wherein said second diagnostic control means comprises an error storing means, a control register for receiving diagnostic control information from said means for generating address signals and generating a diagnostic control signal and a multiplexer responsive to said diagnostic control signal and having an input connected to said board select signal generating means and an output connected to said error signal storing means.

Claim 15

Apparatus for determining the physical location of a faulty memory component according to claim 10 wherein said means for generating and error signal comprises an error circuit on said board.

Claim 16

Apparatus for determining the physical location of a faulty memory component according to claim 10 wherein said multiplexer has a pair of inputs, one from said board select signal generating means and the other from said error circuit, the output of said multiplexer coupled to said error storing means on the board.

Claim 17

Apparatus for determining the physical location of a faulty memory component according to claim 9 wherein said error signal receiving and storing means comprises an error signal register.

Claim 18

Apparatus for determining the physical location of a faulty board in a computer system that has a plurality of boards, said computer system having a memory and a central means for generating address signals, said apparatus comprising: means for generating an error signal representative of a fault in a mounting board, means for storing said error signal, means responsive to said error signal for storing the address signal corresponding to the location causing said error signal, means located on each of said boards and responsive to said address signal for generating a board select signal, and means responsive to said board select signal for storing a signal representative of the faulty board, said means for storing the address signals reapplying the address signals to all boards for the purpose of determining the faulty board.

Claim 19

Apparatus for determining the physical location of a faulty board in a computer system that has a plurality of boards, said computer system having a memory and a central means for generating address signals, said apparatus comprising: means for generating an error signal representative of a fault in a mounting board, means for storing said error signal, means responsive to said error signal for storing the address signal corresponding to the location causing said error signal, means located on each of said boards and responsive to said address signal for generating a board select signal, and means responsive to said board select signal for storing a signal representative of the faulty board, said means for storing the address signals reapplying the address signals to all boards for the purpose of determining the faulty board.