Availability and diagnostic apparatus for memory modules

Claim 2

A memory module for use in association with a data processing unit comprsiing: comprising: an array of memory elements for storing logic signals; a plurality of driver networks coupled to said memory element array for manipulation of said logic signals; means for producing error correcting code signals for a group of said logic signals, said code signals and said logic signal group being thereafter stored in said memory element array, said error correcting means correcting an error in said stored group of logic signals determined by said stored code signals and said stored group of logic signals upon extraction from said memory element array of said stored group of logic signals and said code signals, said stored code signals and said stored group of logic signals being combined to form a group of location-identifying signals; and a maintenance status register coupled to said plurality of driver networks and said error correcting means, said maintenance status register storing first signals identifying the occurrence and location of a driver network malfunction, said maintenance status register storing second signals identifying the occurrence and said location-identifying signals of an error in said stored group of logic signal.

Claim 3

The memory module of claim 1 wherein said maintenance status register includes a means for counting signals, said maintenance status register storing the count of signals produced by correction of errors for said groups of logic signals.

Claim 4

The memory module of claim 2 further including means for detection of errors in a group of logic signals entering said memory module by means of associated parity check signals, each of said parity check signals associated with a predetermined portion of said group of logic signals, said error detecting means coupled to said maintenance status register, said maintenance status register storing third error signals identifying the occurrence and said predetermined portion containing said error in said entering group of logic signals.

Claim 5

The memory module of claim 3 further comprising: means for addressing a preselected portion of said memory element array, said preselected portion of said memory element array determined by address data from said data processing unit, said address means coupled to said maintenance status register and said driver circuits, said address means including parity check apparatus for verification of said address data, said address means delivering at least one fifth signal for storage in said maintenance status register upon identification of an error in said address data.

Claim 6

The memory module of claim 4 further including: refresh means for restoring said logic signals in said memory element array, said refresh means coupled to said address means and said maintenance status register, said maintenance status register storing information verifying operation of said refresh means controlled by said data processing unit.

Claim 7

The memory module of claim 5 wherein said maintenance status register is comprised of a plurality of semiconductor element storage networks.

Claim 8

The memory module of claim 6 wherein said memory element array is comprised of metal-oxide-semiconductor elements.

Claim 9

The memory module of claim 6, wherein said first signals replace other signals stored in said maintenance status registEr upon identification of a driver circuit malfunction.

Claim 10

The memory module of claim 8 wherein said maintenance status register stores fourth signals specifying a mode of operation of said memory module, said modes including a normal mode, a mode wherein said error correcting means is by-passed, a mode wherein said error correcting means and said checking means are by-passed and refresh diagnostic mode.

Claim 11

For use in association with a data processing unit, memory module comprising: a maintenance status register coupled to said data processing unit, said maintenance status register including a plurality of signal storage networks, said maintenance status register signalling to said data processing unit an occurrence of an error; error checking-correction means for producing parity checks on subgroups of an incoming data group with associated parity check signals, said error checking-correcting means for providing said incoming data group with ECC check bits, said error checking-correction means for correcting outgoing data from said ECC check bits said error checking-correcting means for adding parity signals for subgroup of said outgoing data, wherein an occurrence and a location of a error in said outgoing data is signaled to a second group of said signal storage networks, a more recent error in said outgoing data replacing signals from a previously corrected error; a plurality of memory elements coupled to said error checking correcting means for storing said incoming data group; driver circuits coupled to said memory elements to said data processing unit and to said maintenance status register, wherein said driver circuits electrically control said memory elements in response to control signals from said data processing unit, signals designating an occurrence and a location of a malfunction of one of said driver circuits replacing signals stored in said second group of signal storage networks.

Claim 12

For use in association with a data processing unit, memory module comprising: a maintenance status register coupled to said data processing unit, said maintenance status register including a plurality of signal storage networks, said maintenance status register signalling to said data processing unit an occurrence of an error; error checking-correction means for producing parity checks on subgroups of an incoming data group with associated parity check signals, said error checking-correcting means for providing said incoming data group with ECC check bits, said error checking-correction means for correcting outgoing data from said ECC check bits said error checking-correcting means for adding parity signals for subgroup of said outgoing data, wherein an occurrence and a location of a error in said outgoing data is signaled to a second group of said signal storage networks, a more recent error in said outgoing data replacing signals from a previously corrected error; a plurality of memory elements coupled to said error checking correcting means for storing said incoming data group; driver circuits coupled to said memory elements to said data processing unit and to said maintenance status register, wherein said driver circuits electrically control said memory elements in response to control signals from said data processing unit, signals designating an occurrence and a location of a malfunction of one of said driver circuits replacing signals stored in said second group of signal storage networks.

Claim 13

The memory module of claim 10 wherein said maintenance status register includes a counter means for counting a number of errors corrected in groups of said outgoing data, wherein said number of errors specifies a choice between normal operation of error checking correcting means and a deteriorating memory element.

Claim 14

The memory module of claim 11, further comprising: refresh means for controlling restoration of signals stored in said memory elements; said refresh means coupled to said driver circuits and to said maintenance status register, said refresh means tested in response to control signals from said data processing unit, said refresh means producing signals stored said second group of storage networks upon a malfunction of said refresh means; and wherein signals resulting from an occurrence and a location during said refresh means testing of a malfunction of said driver circuits replaces said signals stored in said second group of storage networks.

Claim 15

The memory module of claim 12, wherein said incoming data group contains a plurality of data subgroups, said first group of storage networks also containing signals identifying a one of said data subgroups containing an error.

Claim 16

The memory module of claim 13, further comprising: address means for controlling an address of a group of memory element corresponding to a one of said data groups, said address apparatus, coupled to said data processing unit, said driver circuits and said memory elements, said address means checking address data from said data processing unit for errors and storing a location of said address data error in a third group of storage networks.

Claim 17

The apparatus of claim 14 wherein storing of error information is said storage networks causes a first signal to be applied to said data processing unit upon correction of said outgoing data group cause a second signal to be applied to said data processing upon detection of errors in said incoming data groups and causing a third signal to be applied to said data processing unit upon detection of saiD driver circuit malfunction.

Claim 18

The memory module of claim 15 further comprising means for applying signals stored in said maintenance status register to said data processing unit in response to a command signal from said data processing unit.

Claim 19

The memory module of claim 9 further comprising means for applying signals stored in maintenance status register to said data processing unit in response to a command signal from said data processing unit.

Claim 20

In association with a data processing unit, an improved memory module having an array of memory elements, error checking apparatus, error-correcting-code apapratus, driver circuits and an address control unit, wherein the improvement comprises: a maintenance status register coupled to said data processing unit, said error correcting means, said driver circuits, and said address control unit, said maintenance status register storing information localizing errors in incoming data signals localizing errors arising in said memory element, and storing information localizing malfunctions of said drive circuits.

Claim 21

In association with a data processing unit, an improved memory module having an array of memory elements, error checking apparatus, error-correcting-code apapratus, driver circuits and an address control unit, wherein the improvement comprises: a maintenance status register coupled to said data processing unit, said error correcting means, said driver circuits, and said address control unit, said maintenance status register storing information localizing errors in incoming data signals localizing errors arising in said memory element, and storing information localizing malfunctions of said drive circuits.

Claim 22

The improved memory module of claim 18 further comprising means for differentiating between normal operation of said ECC equipment and an operation correcting for a deteriorating memory element, said differentiation means contained within said maintenance status register.

Claim 23

In association with a data processing unit, an improved memory module having an array of memory elements and means for restoring logic signals stored in said memory elements, wherein the improvement comprises: a maintenance status register coupled to said data processing unit and to said restoration means, wherein said restoration means is tested under control of said data processing unit, said maintenance status register storing information which localizes errors in said restoration means during said testing, said information which localizes errors in said restoration means replaced by information which localizes a malfunction in said driver circuit during said testing.

Claim 24

In association with a data processing unit, an improved memory module having an array of memory elements and means for restoring logic signals stored in said memory elements, wherein the improvement comprises: a maintenance status register coupled to said data processing unit and to said restoration means, wherein said restoration means is tested under control of said data processing unit, said maintenance status register storing information which localizes errors in said restoration means during said testing, said information which localizes errors in said restoration means replaced by information which localizes a malfunction in said driver circuit during said testing.

Claim 25

The memory module of claim 20, wherein said restoration means includes a plurality of modes of operation for restoring said logic signals, each of said modes actuated by a predetermined group of signals from said data processing unit, and wherein information identifying said mode is stored in said maintenance status register along with said error signals.

Claim 26

In association with a data processing unit, an improved memory module having a plurality of memory elements, address control means for addressing a preselected group of said memory elements, driver circuits for manipulation of said memory elements, parity checking means and error-correcting code (ECC) apparatus wherein the improvement comprises: a maintenance status register for storing error information including, in adjacency to each other: means for storing information identifying an occurrence and a location of a driver circuit malfunction, means for storing information identifying an occurrence and a location of data error detected by said ECC apparatus, means for counting and storing information identifying each of said data errors detected by said ECC apparatus, means for storing information identifying an occurrence and specifying a group of incoming data containing a parity error, means for storing information identifying an error in address data, means for storing information identifying a mode of operation presently controlling said memory module operation, and means for transferring said stored error information to said data processing unit, said transferral means connected to each of said storage means and to said data processing unit.

Claim 27

In association with a data processing unit, an improved memory module having a plurality of memory elements, address control means for addressing a preselected group of said memory elements, driver circuits for manipulation of said memory elements, parity checking means and error-correcting code (ECC) apparatus wherein the improvement comprises: a maintenance status register for storing error information including, in adjacency to each other: means for storing information identifying an occurrence and a location of a driver circuit malfunction, means for storing information identifying an occurrence and a location of data error detected by said ECC apparatus, means for counting and storing information identifying each of said data errors detected by said ECC apparatus, means for storing information identifying an occurrence and specifying a group of incoming data containing a parity error, means for storing information identifying an error in address data, means for storing information identifying a mode of operation presently controlling said memory module operation, and means for transferring said stored error information to said data processing unit, said transferral means connected to each of said storage means and to said data processing unit.

Claim 28

The improved memory module of claim 22 further having refresh means for restoration of signals in said memory elements, said refresh means connected to said maintenance status register and to said memory elements, said maintenance status register further including means for Storing information identifying an occurrence and location of an error produced by said refresh means during a test procedure under control of said data processing unit.