US3735105A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Error correcting system and method for monolithic memories
Assignee: International Business Machines Corp
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Filing: 1971-06-11
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Granted: 1973-05-22
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Expires: 1991-06-11
Abstract
Abstract A memory correcting system in accordance with this disclosure is an integral part of a digital electronic computer having a monolithic memory. The memory correcting system detects, records and analyzes errors occurring during normal operation of the computer. Also, the memory correcting system systematically addresses the monolithic memory on a cycle stealing basis monitoring the general health of the monolithic memory. The systematic reading and writing of all monolithic memory locations prevents the accumulating effects of random errors. By detecting single errors as rapidly as possible, the probability of acquiring additional errors that are above the correcting capabilities of the redundancy code are avoided.
Inventors
- 👤 G Maley
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 16:57
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/10; G06F11/1008; G06F11/0703; G06F11/0706; G06F11/073; G06F11/0766; G06F11/0772; G06F11/1076; G11; G11C; G11C11/00; G11C29/00; G11C29/04; G11C29/08; G11C29/48
Claims Analysis
Total Claims: 38
Claim 1
Independent Claim
371 words
In a programmable electronic digital computer having a central processing unit operable in accordance with a main computer program, said central processing unit being electrically connectable to one or more input/output devices for transfer of digital signals, the combination comprising: a priority circuit operatively associated with said central processing unit and said one or more input/output devices and responsive to control signals from said central processing unit and said one or more input/output devices, said priority circuit providing a priority gating signal indicative of which one of the input/output devices or central processing unit is to address the monolithic memory at a particular instant of time; addressing means operatively associated with the priority circuit and responsive to the priority gating signal from the priority circuit, determining whether one of the input/output devices, or the central processing unit is to address the monolithic memory at a particular instant of time, said addressing means also being operatively associated with each of said one or more input/output devices and said central processing unit and responsive to an addressing signal when the priority circuit indicates a corresponding priority gating signal; a monolithic memory operatively associated with said addressing means and responsive to address signals from said addressing means for transferring digital signals stored in the monolithic memory at a particular location indicated by the address signals; a parity correcting circuit operatively associated with said monolithic memory and responsive to an output signal from said monolithic memory for determining the correctness of information including data bits and check bits read from the monolithic memory; a memory correcting system operatively associated with the priority circuit and providing an address to the addressing means whenever the priority circuit determines that neither the central processing unit nor any of the one or more input/output devices is to address the monolithic memory at that particular inStant of time, said memory correcting system being also operatively associated with the parity correcting circuit and receiving a signal from said parity correcting circuit whenever a parity error is corrected, said memory correcting system being also operatively associated with the monolithic memory and receiving and storing output signals from the monolithic memory whenever the parity correcting circuit indicates that a parity error is corrected.
Claim 2
Dependent Claim
371 words
In a programmable electronic digital computer having a central processing unit operable in accordance with a main computer program, said central processing unit being electrically connectable to one or more input/output devices for transfer of digital signals, the combination comprising: a priority circuit operatively associated with said central processing unit and said one or more input/output devices and responsive to control signals from said central processing unit and said one or more input/output devices, said priority circuit providing a priority gating signal indicative of which one of the input/output devices or central processing unit is to address the monolithic memory at a particular instant of time; addressing means operatively associated with the priority circuit and responsive to the priority gating signal from the priority circuit, determining whether one of the input/output devices, or the central processing unit is to address the monolithic memory at a particular instant of time, said addressing means also being operatively associated with each of said one or more input/output devices and said central processing unit and responsive to an addressing signal when the priority circuit indicates a corresponding priority gating signal; a monolithic memory operatively associated with said addressing means and responsive to address signals from said addressing means for transferring digital signals stored in the monolithic memory at a particular location indicated by the address signals; a parity correcting circuit operatively associated with said monolithic memory and responsive to an output signal from said monolithic memory for determining the correctness of information including data bits and check bits read from the monolithic memory; a memory correcting system operatively associated with the priority circuit and providing an address to the addressing means whenever the priority circuit determines that neither the central processing unit nor any of the one or more input/output devices is to address the monolithic memory at that particular inStant of time, said memory correcting system being also operatively associated with the parity correcting circuit and receiving a signal from said parity correcting circuit whenever a parity error is corrected, said memory correcting system being also operatively associated with the monolithic memory and receiving and storing output signals from the monolithic memory whenever the parity correcting circuit indicates that a parity error is corrected.
Claim 3
Dependent Claim
47 words
Apparatus as in claim 1 in which the memory correcting system further comprises: means responsive to the priority circuit for determining particular intervals of time when the monolithic memory is not busy; and means for sequentially addressing the monolithic memory during the said particular intervals of time.
Claim 4
Dependent Claim
20 words
Apparatus as in claim 2 in which the means for sequentially addressing the monolithic memory comprises: an electronic counting circuit.
Claim 5
Dependent Claim
297 words
In an electronic digital computer having a central processing unit operable by a main program, one or more input/output devices electrically connectable to the central processing unit for transfer of digital signals including information and control signals, and having a monolithic memory with information and control inputs and outputs adapted to receive and provide digital signals including information and control signals from and to said central processing unit and said input/output devices, said monolithic memory adapted to store information signals from said central processing unit and said input/output devices and for providing said information signals at an information output when said monolithic memory receives control signals at its control input, priority circuit responsive to digital signals from said central processing unit and said one or more input/output devices for determining which one of said one or more input/output devices or said central processing unit is to address the monolithic memory, a parity correcting circuit responsive to an information output of the monolithic memory for detecting and correcting parity errors in said output signal, the improvement including a memory correcting system, the said memory correcting system comprising: gating means responsive to the priority circuit for actuating means for sequentially addressing the monolithic memory whenever the priority circuit indicates that neither the central processing unit nor the one or more input devices is to address the monolithic memory; means responsive to the parity correcting circuit for gating information from the monolithic memory and its corresponding address into the memory correcting system when the parity correcting circuit indicates that an error has been corrected; means for storing errored data and its corresponding address; and means for diagnosing detected errors and for providing a program interrupt output to the central processing unit when the diagnosis indicates the need for such interruption.
Claim 6
Dependent Claim
297 words
In an electronic digital computer having a central processing unit operable by a main program, one or more input/output devices electrically connectable to the central processing unit for transfer of digital signals including information and control signals, and having a monolithic memory with information and control inputs and outputs adapted to receive and provide digital signals including information and control signals from and to said central processing unit and said input/output devices, said monolithic memory adapted to store information signals from said central processing unit and said input/output devices and for providing said information signals at an information output when said monolithic memory receives control signals at its control input, priority circuit responsive to digital signals from said central processing unit and said one or more input/output devices for determining which one of said one or more input/output devices or said central processing unit is to address the monolithic memory, a parity correcting circuit responsive to an information output of the monolithic memory for detecting and correcting parity errors in said output signal, the improvement including a memory correcting system, the said memory correcting system comprising: gating means responsive to the priority circuit for actuating means for sequentially addressing the monolithic memory whenever the priority circuit indicates that neither the central processing unit nor the one or more input devices is to address the monolithic memory; means responsive to the parity correcting circuit for gating information from the monolithic memory and its corresponding address into the memory correcting system when the parity correcting circuit indicates that an error has been corrected; means for storing errored data and its corresponding address; and means for diagnosing detected errors and for providing a program interrupt output to the central processing unit when the diagnosis indicates the need for such interruption.
Claim 7
Dependent Claim
249 words
A programmable electronic digital computer operable in accordance with a main computer program and having a central processing unit, at least one input/output device electrically connectable to said processing unit for transferring digital signals, and also having a monolithic memory for storing digital signals received from either said central processing unit or said at least one input/output device, said monolithic memory receiving digital signals to be stored from either said central processing unit or said at least one input/output device, said monolithic memory receiving control signals from an addressing means, said addressing means receiving signals from said central processing unit and from said at least one input/output device, said addressing means also receiving an input from a priority circuit said priority circuit receiving an input from said central processing unit and said at least one input/output device, the improvement comprising: an error-detecting circuit receiving output information from said monolithic memOry, for determining the correctness of said output information and for providing an error-indicating signal to a memory correcting system; and a memory correcting system receiving the output of said error detecting circuit, said memory correcting system also receiving the output of said monolithic memory, said memory correcting system also receiving an input from said addressing means, said memory correcting system providing an output to said addressing means for addressing said monolithic memory when the priority circuit indicates that neither the central processing unit nor the said at least one input/output device is providing a signal to said priority circuit.
Claim 8
Dependent Claim
249 words
A programmable electronic digital computer operable in accordance with a main computer program and having a central processing unit, at least one input/output device electrically connectable to said processing unit for transferring digital signals, and also having a monolithic memory for storing digital signals received from either said central processing unit or said at least one input/output device, said monolithic memory receiving digital signals to be stored from either said central processing unit or said at least one input/output device, said monolithic memory receiving control signals from an addressing means, said addressing means receiving signals from said central processing unit and from said at least one input/output device, said addressing means also receiving an input from a priority circuit said priority circuit receiving an input from said central processing unit and said at least one input/output device, the improvement comprising: an error-detecting circuit receiving output information from said monolithic memOry, for determining the correctness of said output information and for providing an error-indicating signal to a memory correcting system; and a memory correcting system receiving the output of said error detecting circuit, said memory correcting system also receiving the output of said monolithic memory, said memory correcting system also receiving an input from said addressing means, said memory correcting system providing an output to said addressing means for addressing said monolithic memory when the priority circuit indicates that neither the central processing unit nor the said at least one input/output device is providing a signal to said priority circuit.
Claim 9
Dependent Claim
46 words
Apparatus as in claim 5 wherein said memory correcting system further comprises: recording means for recording the output signal from said monolithic memory and the address of said output signal from the addressing means when said error detecting circuit determines that an error has been detected.
Claim 10
Dependent Claim
43 words
Apparatus as in claim 6 wherein said memory correcting system includes gating means, said gating means receiving an output from said error detecting means and gating the output of said monolithic memory and the output from said addressing means into a recording means.
Claim 11
Dependent Claim
22 words
Apparatus as in claim 7 wherein said memory correcting system includes a mini-computer for analyzing the information stored in said recording means.
Claim 12
Dependent Claim
78 words
Apparatus as in claim 5 wherein said memory correcting system includes gating means for receiving an output from said priority circuit and for receiving an inverted output from said error detecting means, and for providing an output signal to a systematic addressing means whenever the priority circuit indicates that neither the central processing unit nor any other said input/output devices desires to address the monolithic memory and also the error detecting circuit indicates that no error was detected.
Claim 13
Dependent Claim
216 words
In an electronic digital computer having a central processing unit operable in accordance with a main computer program and having input/output devices electrically connectable to the central processing unit for insertion and extraction of digital signals including information and control signals, and having a monolithic memory with information and control inputs adapted to receive digital signals including information and control signals from said central processing unit and said input/output devices, the combination further comprising: addressing means electrically connected to the control inputs of said monolithic memory for accessing a particular portion of said monolithic memory; a priority circuit receiving an input from both said central processing unit and said input/output devices for providing an input to said addressing means, thereby determining whether said central processing unit or one of said input/output devices addresses the monolithic memory at a particular instant of time; a parity correcting circuit for receiving output information from said monolithic memory and determining the correctness of said output information; and a memory correcting system receiving an input from the parity correcting circuit and also receiving an input from the monolithic memory; said memory correcting system including means for recording the output of the monolithic memory and its address whenever the parity correcting circuit determines that the output of said monolithic memory is incorrect.
Claim 14
Dependent Claim
216 words
In an electronic digital computer having a central processing unit operable in accordance with a main computer program and having input/output devices electrically connectable to the central processing unit for insertion and extraction of digital signals including information and control signals, and having a monolithic memory with information and control inputs adapted to receive digital signals including information and control signals from said central processing unit and said input/output devices, the combination further comprising: addressing means electrically connected to the control inputs of said monolithic memory for accessing a particular portion of said monolithic memory; a priority circuit receiving an input from both said central processing unit and said input/output devices for providing an input to said addressing means, thereby determining whether said central processing unit or one of said input/output devices addresses the monolithic memory at a particular instant of time; a parity correcting circuit for receiving output information from said monolithic memory and determining the correctness of said output information; and a memory correcting system receiving an input from the parity correcting circuit and also receiving an input from the monolithic memory; said memory correcting system including means for recording the output of the monolithic memory and its address whenever the parity correcting circuit determines that the output of said monolithic memory is incorrect.
Claim 15
Dependent Claim
215 words
In an electronic digital computer having a central processing unit operable in accordance with a main computer program and having input/output devices electrically connectable to the central processing unit for transfer of digital signals including information and control signals, and having a monolithic memory with information and control inputs adapted to receive digital signals including information and control signals from said central processing unit and said input/output devices, with the combination further comprising: addressing means electrically Connected to the control input of said monolithic memory for accessing a particular portion of said monolithic memory; a priority circuit receiving an input from said central processing unit and said input/output devices for providing an input to said addressing means, thereby determining whether said central processing unit or one of said input/output devices is to address the monolithic memory at a particular instant of time; a memory correcting system operatively associated with said priority circuit and responsive to an output of said priority circuit indicating that neither the central processing unit nor the input/output devices are addressing the monolithic memory, said memory correcting system including means for systematically providing an input address to said addressing means so long as the priority circuit indicates that neither the central processing unit nor the input/output devices are addressing the monolithic memory.
Claim 16
Dependent Claim
215 words
In an electronic digital computer having a central processing unit operable in accordance with a main computer program and having input/output devices electrically connectable to the central processing unit for transfer of digital signals including information and control signals, and having a monolithic memory with information and control inputs adapted to receive digital signals including information and control signals from said central processing unit and said input/output devices, with the combination further comprising: addressing means electrically Connected to the control input of said monolithic memory for accessing a particular portion of said monolithic memory; a priority circuit receiving an input from said central processing unit and said input/output devices for providing an input to said addressing means, thereby determining whether said central processing unit or one of said input/output devices is to address the monolithic memory at a particular instant of time; a memory correcting system operatively associated with said priority circuit and responsive to an output of said priority circuit indicating that neither the central processing unit nor the input/output devices are addressing the monolithic memory, said memory correcting system including means for systematically providing an input address to said addressing means so long as the priority circuit indicates that neither the central processing unit nor the input/output devices are addressing the monolithic memory.
Claim 17
Dependent Claim
182 words
In an electronic digital computer having a central processing unit operable in accordance with a main computer program and having input/output devices electrically connectable to the central processing unit for insertion and extraction of digital signals including information and control signals, and having a monolithic memory with information and control inputs adapted to receive digital signals including information and control signals from said central processing unit and said input/output devices, the combination further comprising: addressing means electrically connected to the control input of said monolithic memory for accessing a particular portion of said monolithic memory; a parity correcting circuit for receiving output information from said monolithic memory and determining the correctness of said output information; and a memory correcting system operatively associated with said parity correcting circuit and responsive to the output of said parity correcting circuit, said memory correcting system also operatively associated with the monolithic memory and responsive to said output information from said monolithic memory, said memory correcting system including recording means for recording said output information whenever said parity correcting circuit determines that said output information is incorrect.
Claim 18
Dependent Claim
182 words
In an electronic digital computer having a central processing unit operable in accordance with a main computer program and having input/output devices electrically connectable to the central processing unit for insertion and extraction of digital signals including information and control signals, and having a monolithic memory with information and control inputs adapted to receive digital signals including information and control signals from said central processing unit and said input/output devices, the combination further comprising: addressing means electrically connected to the control input of said monolithic memory for accessing a particular portion of said monolithic memory; a parity correcting circuit for receiving output information from said monolithic memory and determining the correctness of said output information; and a memory correcting system operatively associated with said parity correcting circuit and responsive to the output of said parity correcting circuit, said memory correcting system also operatively associated with the monolithic memory and responsive to said output information from said monolithic memory, said memory correcting system including recording means for recording said output information whenever said parity correcting circuit determines that said output information is incorrect.
Claim 19
Dependent Claim
76 words
Apparatus as in claim 12 wherein said addressing means comprises: an address gate adapted to receive input signals from the central processing unit, from the input/output devices, from the memory correcting system, and from the priority circuit; a memory address register responsive to said address gate and providing signals to said memory correcting system and a decoder: the decoder being responsive to signals from said memory address register and providing an output to said monolithic memory.
Claim 20
Dependent Claim
370 words
In a programmable electronic digital computer having a central processing unit operable in accordance with a main computer program, said central processing unit being electrically connectable to one or more input/output devices for transfer of digital signals, the combination comprising: a priority circuit operatively associated with said central processing unit and said one or more input/output devices and responsive to control signals from said central processing unit and said one or more input/output devices, said priority circuit providing a priority gating signal indicative of which one of the input/output devices or central processing unit is to address the monolithic memory at a particular instant of time; addressing means operatively associated with the priority circuit and responsive to the priority gating signal from the priority circuit, determining whether one of the input/output devices, or the central processing unit is to address the monolithic memory at a particular instant of time, said addressing means also being operatively associated with each of said one or more input/output devices and said central processing unit and responsive to an addressing signal when the priority circuit indicates a corresponding priority gating signal; a monolithic memory operatively associated with said addressing means and responsive to address signals from said addressing means for transferring digital signals stored in the monolithic memory at a particular location indicated by the address signals; an error detecting circuit operatively associated with said monolithic memory and responsive to an output signal from said monolithic memory for determining the correctness of information including data bits and check bits read from the monolithic memory; a memory correcting system operatively associated with the priority circuit and systematically providing an address to the addressing means whenever the priority circuit determines that neither the central processing unit nor any of the one or more input/output devices is to address the monolithic memory at that particular instant of time, said memory correcting system being also operatively associated with the error detecting circuit and receiving a signal from said error detecting circuit whenever an error is detected, said memory correcting system being also operatively associated with the monolithic memory and receiving and storing output signals from the monolithic memory whenever the error detecting circuit indicates that an error is detected.
Claim 21
Dependent Claim
370 words
In a programmable electronic digital computer having a central processing unit operable in accordance with a main computer program, said central processing unit being electrically connectable to one or more input/output devices for transfer of digital signals, the combination comprising: a priority circuit operatively associated with said central processing unit and said one or more input/output devices and responsive to control signals from said central processing unit and said one or more input/output devices, said priority circuit providing a priority gating signal indicative of which one of the input/output devices or central processing unit is to address the monolithic memory at a particular instant of time; addressing means operatively associated with the priority circuit and responsive to the priority gating signal from the priority circuit, determining whether one of the input/output devices, or the central processing unit is to address the monolithic memory at a particular instant of time, said addressing means also being operatively associated with each of said one or more input/output devices and said central processing unit and responsive to an addressing signal when the priority circuit indicates a corresponding priority gating signal; a monolithic memory operatively associated with said addressing means and responsive to address signals from said addressing means for transferring digital signals stored in the monolithic memory at a particular location indicated by the address signals; an error detecting circuit operatively associated with said monolithic memory and responsive to an output signal from said monolithic memory for determining the correctness of information including data bits and check bits read from the monolithic memory; a memory correcting system operatively associated with the priority circuit and systematically providing an address to the addressing means whenever the priority circuit determines that neither the central processing unit nor any of the one or more input/output devices is to address the monolithic memory at that particular instant of time, said memory correcting system being also operatively associated with the error detecting circuit and receiving a signal from said error detecting circuit whenever an error is detected, said memory correcting system being also operatively associated with the monolithic memory and receiving and storing output signals from the monolithic memory whenever the error detecting circuit indicates that an error is detected.
Claim 22
Dependent Claim
370 words
In a programmable electronic digital computer having a central processing unit operable in accordance with a main computer program, said central processing unit being electrically connectable to one or more input/output devices for transfer of digital signals, the combination comprising: a priority circuit operatively associated with said central processing unit and said one or more input/output devices and responsive to control signals from said central processing unit and said one or more input/output devices, said priority circuit providing a priority gating signal indicative of which one of the input/output devices or central processing unit is to address the monolithic memory at a particular instant of time; addressing means operatively associated with the priority circuit and responsive to the priority gating signal from the priority circuit, determining whether one of the input/output devices, or the central processing unit is to address the monolithic memory at a particular instant of time, said addressing means also being operatively associated with each of said one or more input/output devices and said central processing unit and responsive to an addressing signal when the priority circuit indicates a corresponding priority gating signal; a monolithic memory operatively associated with said addressing means and responsive to address signals from said addressing means for transferring digital signals stored in the monolithic memory at a particular location indicated by the address signals; an error detecting circuit operatively associated with said monolithic memory and responsive to an output signal from said monolithic memory for determining the correctness of information including data bits and check bits read from the monolithic memory; a memory correcting system operatively associated with the priority circuit and sequentially providing an address to the addressing means whenever the priority circuit determines that neither the central processing unit nor any of the one or more input/output devices is to address the monolithic memory at that particular instant of time, said memory correcting system being also operatively associated with the error detecting circuit and receiving a signal from said error detecting circuit whenever an error is detected, said memory correcting system being also operatively associated with the monolithic memory and receiving and storing output signals from the monolithic memory whenever the error detecting circuit indicates that an error is detected.
Claim 23
Dependent Claim
370 words
In a programmable electronic digital computer having a central processing unit operable in accordance with a main computer program, said central processing unit being electrically connectable to one or more input/output devices for transfer of digital signals, the combination comprising: a priority circuit operatively associated with said central processing unit and said one or more input/output devices and responsive to control signals from said central processing unit and said one or more input/output devices, said priority circuit providing a priority gating signal indicative of which one of the input/output devices or central processing unit is to address the monolithic memory at a particular instant of time; addressing means operatively associated with the priority circuit and responsive to the priority gating signal from the priority circuit, determining whether one of the input/output devices, or the central processing unit is to address the monolithic memory at a particular instant of time, said addressing means also being operatively associated with each of said one or more input/output devices and said central processing unit and responsive to an addressing signal when the priority circuit indicates a corresponding priority gating signal; a monolithic memory operatively associated with said addressing means and responsive to address signals from said addressing means for transferring digital signals stored in the monolithic memory at a particular location indicated by the address signals; an error detecting circuit operatively associated with said monolithic memory and responsive to an output signal from said monolithic memory for determining the correctness of information including data bits and check bits read from the monolithic memory; a memory correcting system operatively associated with the priority circuit and sequentially providing an address to the addressing means whenever the priority circuit determines that neither the central processing unit nor any of the one or more input/output devices is to address the monolithic memory at that particular instant of time, said memory correcting system being also operatively associated with the error detecting circuit and receiving a signal from said error detecting circuit whenever an error is detected, said memory correcting system being also operatively associated with the monolithic memory and receiving and storing output signals from the monolithic memory whenever the error detecting circuit indicates that an error is detected.
Claim 24
Dependent Claim
64 words
Apparatus as in claim 1 in which said monolithic memory is arranged on a plurality of semiconductor chips and moduleS and said memory correcting system operatively associated with the priority circuit systematically providing addresses to the addressing means such that addresses associated with individual chips and modules are accessed in sequence thereby readily identifying faulty ones of said plurality of semiconductor chips and modules.
Claim 25
Dependent Claim
76 words
Apparatus as in claim 1 wherein said addressing means comprises: an address gate adapted to receive input signals from the central processing unit, from the input/output devices, from the memory correcting system, and from the priority circuit; a memory address register responsive to said address gate and providing signals to said memory correcting system and a decoder: the decoder being responsive to signals from said memory address register and providing an output to said monolithic memory.
Claim 26
Dependent Claim
298 words
In an electronic digital computer having a central processing unit operable by a main program, one or more input/output devices electrically connectable to the central processing unit for transfer of digital signals including information and control signals, and having a monolithic memory with information and control inputs and outputs adapted to receive and provide digital signals including information and control signals from and to said central processing unit and said input/output devices, said monolithic memory adapted to store information signals from said central processing unit and said input/output devices and for providing said information signals at an information output when said monolithic memory receives control signals at its control input, a priority circuit responsive to digital signals from said central processing unit and said one or more input/output devices for determining which one of said one or more input/output devices or said central processing unit is to address the monolithic memory, a parity correcting circuit responsive to an information output of the monolithic memory for detecting and correcting parity errors in said output signal, the improvement including a memory correcting system, the said memory correcting system comprising: gating means responsive to the priority circuit for actuating means for systematically addressing the monolithic memory whenever the priority circuit indicates that neither the central processing unit nor the one or more input devices is to address the monolithic memory; means responsive to the parity correcting circuit for gating information from the monolithic memory and its corresponding address into the memory correcting system when the parity correcting circuit indicates that an error has been corrected; means for storing errored data and its corresponding address; and means for diagnosing detected errors and for providing a program interrupt output to the central processing unit when the diagnosis indicates the need for such interruption.
Claim 27
Dependent Claim
298 words
In an electronic digital computer having a central processing unit operable by a main program, one or more input/output devices electrically connectable to the central processing unit for transfer of digital signals including information and control signals, and having a monolithic memory with information and control inputs and outputs adapted to receive and provide digital signals including information and control signals from and to said central processing unit and said input/output devices, said monolithic memory adapted to store information signals from said central processing unit and said input/output devices and for providing said information signals at an information output when said monolithic memory receives control signals at its control input, a priority circuit responsive to digital signals from said central processing unit and said one or more input/output devices for determining which one of said one or more input/output devices or said central processing unit is to address the monolithic memory, a parity correcting circuit responsive to an information output of the monolithic memory for detecting and correcting parity errors in said output signal, the improvement including a memory correcting system, the said memory correcting system comprising: gating means responsive to the priority circuit for actuating means for systematically addressing the monolithic memory whenever the priority circuit indicates that neither the central processing unit nor the one or more input devices is to address the monolithic memory; means responsive to the parity correcting circuit for gating information from the monolithic memory and its corresponding address into the memory correcting system when the parity correcting circuit indicates that an error has been corrected; means for storing errored data and its corresponding address; and means for diagnosing detected errors and for providing a program interrupt output to the central processing unit when the diagnosis indicates the need for such interruption.
Claim 28
Dependent Claim
114 words
In a programmable electronic computer, the combination comprising: a monolithic memory; input means for transferring information signals into the said monolithic memory; an error detecting means operatively associated with said monolithic memory and responsive to output information signals from said monolithic memory, for providing a signal indicative of an error to a memory correcting system; said memory correcting system having an input responsive to said signal indicative of an error, said memory correcting system being also operatively associated with said monolithic memory and responsive to output information signals from said monolithic memory, said memory correcting system further having means for recording said output information signals in response to said signal indicative of an error.
Claim 29
Dependent Claim
114 words
In a programmable electronic computer, the combination comprising: a monolithic memory; input means for transferring information signals into the said monolithic memory; an error detecting means operatively associated with said monolithic memory and responsive to output information signals from said monolithic memory, for providing a signal indicative of an error to a memory correcting system; said memory correcting system having an input responsive to said signal indicative of an error, said memory correcting system being also operatively associated with said monolithic memory and responsive to output information signals from said monolithic memory, said memory correcting system further having means for recording said output information signals in response to said signal indicative of an error.
Claim 30
Dependent Claim
43 words
Apparatus as in claim 19 in which said memory correcting system additionally includes means for systematically addressing said monolithic memory, the combination additionally comprising: addressing means operatively associated with said memory correcting system and responsive to address sigNals from said systematic addressing means.
Claim 31
Dependent Claim
154 words
Apparatus as in claim 20 further comprising: a priority circuit connected to said addressing means and providing a priority gating signal to said addressing means; an input/output device connected to the input of said priority circuit for providing an input to said priority circuit when the input/output device desires access to the monolithic memory; a central processing unit connected to an input of said priority circuit for providing an input signal to said priority circuit when the central processing unit desires access to the monolithic memory; said addressing means being operatively associated with said input/output device and responsive to an address signal therefrom; said addressing means being operatively associated with said central processing unit and responsive to an address signal therefrom; said addressing means providing an address signal from said memory correcting system to said monolithic memory only when neither the input/output device nor said central processing unit desires access to the monolithic memory.
Claim 32
Dependent Claim
158 words
In an electronic digital computer having a central processing unit operable in accordance with a main computer program and having input/output devices electrically connectable to the central processing unit for transfer of digital signals including information and control signals, and having a monolithic memory with information and control inputs adapted to receive digital signals including information and control signals from said central processing unit and said input/output devices, said monolithic memory adapted to store information signals from said central processing unit and said input/output devices and for providing said information signals at its output when said monolithic memory receives control signals at its control inputs, the method comprising the steps of: detecting errors in the information signals at the output of said monolithic memory; providing an error-indicating signal to a memory correcting system when an error is detected; providing the address of the errored data to the memory correcting system; and recording the errored data and its address.
Claim 33
Dependent Claim
158 words
In an electronic digital computer having a central processing unit operable in accordance with a main computer program and having input/output devices electrically connectable to the central processing unit for transfer of digital signals including information and control signals, and having a monolithic memory with information and control inputs adapted to receive digital signals including information and control signals from said central processing unit and said input/output devices, said monolithic memory adapted to store information signals from said central processing unit and said input/output devices and for providing said information signals at its output when said monolithic memory receives control signals at its control inputs, the method comprising the steps of: detecting errors in the information signals at the output of said monolithic memory; providing an error-indicating signal to a memory correcting system when an error is detected; providing the address of the errored data to the memory correcting system; and recording the errored data and its address.
Claim 34
Dependent Claim
168 words
In an electronic digital computer having a central processing unit operable in accordance with a main computer program and having input/output devices electrically connectable to the central processing unit for transfer of digital signals including information and control signals, and having a monolithic memory with information and control inputs adapted to receive digital signals including information and control signals from said central processing unit and said input/output devices, said monolithic memory adapted to store information signals from said central processing unit and said input/output devices and for providing said information signals at its output when said monolithic memory receives control signals at its control inputs, the method comprising the steps of: establishing a priority basis on which the central processing unit and input/output devices address the monolithic memory; providing a memory available signal to a memory correcting system when neither the central processing unit nor any of the input/output devices address the monolithic memory; systematically addressing the monolithic memory during time intervals when memory available signals are provided.
Claim 35
Dependent Claim
168 words
In an electronic digital computer having a central processing unit operable in accordance with a main computer program and having input/output devices electrically connectable to the central processing unit for transfer of digital signals including information and control signals, and having a monolithic memory with information and control inputs adapted to receive digital signals including information and control signals from said central processing unit and said input/output devices, said monolithic memory adapted to store information signals from said central processing unit and said input/output devices and for providing said information signals at its output when said monolithic memory receives control signals at its control inputs, the method comprising the steps of: establishing a priority basis on which the central processing unit and input/output devices address the monolithic memory; providing a memory available signal to a memory correcting system when neither the central processing unit nor any of the input/output devices address the monolithic memory; systematically addressing the monolithic memory during time intervals when memory available signals are provided.
Claim 36
Dependent Claim
28 words
Method as in claim 23 comprising the additional steps of: detecting errors in the output of said monolithic memory; and recording said errored data and its associated address.
Claim 37
Dependent Claim
25 words
Method as in claim 23 in which the step of systematically addressing the monolithic memory is replaced by the step of: sequentially addressing the memory.
Claim 38
Dependent Claim
28 words
Method as in claim 25 comprising the additional steps of: detecting errors in the output of said monolithic memory; and recording said errored data and its associated address.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-05-21 | 1976-11-20 | 1977-05-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-05-21 | 1980-11-20 | 1981-05-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-05-21 | 1984-11-20 | 1985-05-22 | $7700.00 | Window Closed / Lapsed |