Circuit arrangement for recording the addresses of storage cells with erroneous content

Claim 1

A circuit arrangement for recording addresses of storage cells, each of which have data contents that are erroneous with respect to encoding, the storage cells being of a memory configuration connected with a central control unit through a bus system, whereby the circuit arrangement for recording addresses comprises: an error detection circuit which, during an accessing of data of the memory configuration by the central control unit, examines stored data contents read from the storage cells with respect to encoding errors and emits a respective error signal upon a detection of such an encoding error; first recording cells which can be read by the central control unit and which accept at least part of address information occurring on the bus system while the memory configuration is being accessed by the central control unit; second recording cells which can be read by the central control unit and which accept information signals which indicate the type of encoding error detected by the error detection circuit; and a control configuration which, by emitting an input signal at an interrupt input of the central control unit when an error signal is present, causes the control unit to read said first and second recording cells for an evaluation whereby the first recording cells immediately accept, when the memory configuration is accessed for the purpose of reading the data contents of the storage cells, an entire address information forwarded by the central control unit; the second recording cells accept said encoding error type information signals when an error signal is present, and said control configuration is connected with a first interrupt input of the central control unit, which is activated during the fault-free state of the circuit arrangement, and with a second interrupt input with a higher interrupt priority than the first interrupt input, which is deactivated during the fault-free state of the circuit arrangement, such that the control configuration, when an error signal is present, locks out, on one hand, the first recording cells from the reception of additional address information, and on the other hand, starts, through the first interrupt input of the central control unit, a first interrupt routine in the central control unit which serves for determining the presence of dynamic errors and, during the course of the determination, said second interrupt input of the central control unit is activated; and that upon a renewed access by the central control unit of the storage cells designated by the entire address information stored in said first recording cells, the control configuration effects, in the case of another error signal prior to the completion of the first interrupt routine in progress, by means of the second interrupt input which is now activated, an additional interrupt routine for determining static errors.