System for periodically reading all memory locations to detect errors

Claim 2

In a computer system including a solid state memory with a plurality of addressable locations and an error detector/corrector circuit for checking data as it is read from the memory and correcting the data if a detectable error has occurred, the corrected data being stored in the addressed memory location to assure that the correct data is in memory, a circuit to identify all directly addressable memory locations present and to periodically read each present location comprising, in combination: address generator means operative during a search mode for producing each directly addressable memory location; read request means to request, during said search mode, that each address produced by said address generator be read by the memory; storage means responsive to each read request to store an indication from the memory whether the addressed location is present or not present; said address generator operative during a normal run mode to generate periodically all possible directly addressable locations at a rate slower than addresses are generated thereby during said search mode; means operative during normal run mode, and responsive to said storage means and said address generator to initiate a memory read whenever the address produced by said address generator is indicated to be present by the data in said storage means.

Claim 3

In a digital computer system including a memory with a plurality of individually addressable locations, each location for storing data for later retrieval, and a data error detect and a correct circuit for checking the data as it is read from a memory location and correcting the data if a correctable error has occurred, a circuit to identify all present memory locations during a search mode and to periodically read all present memory locations during normal run mode and to correct the data at each present location where a data error is detected on reading the data from the addressable location comprising, in combination: mode defining means alternatively defining a search mode or a normal mode; address generator means responsive to said mode defining means being in said search mode to generate in succession each possible memory address and to apply the produced address to the memory, the memory producing an indication whether the addressed location is present or not present; storage means responsive to said mode defining means being in said search mode to store for each possible memory address, said indication from the memory indicating whether the addressed location is present or not; said mode defining means being responsive to said address generator means having once produced each possible memory address for which said storage means has stored an indication whether the location is present or not to change the mode to said normal mode; said address generator being responsive to said mode defining means being in said normal mode to periodically generate all possible memory addresses at a rate slower than the rate of address generation during said search mode, said address generator being operative to apply said memory address to said memory if said indication in said storage means for said generated address indicates the corresponding memory location is present.

Claim 4

In a digital computer system including a memory with a plurality of individually addressable locations, each location for storing data for later retrieval, and a data error detect and a correct circuit for checking the data as it is read from a memory location and correcting the data if a correctable error has occurred, a circuit to identify all present memory locations during a search mode and to periodically read all present memory locations during normal run mode and to correct the data at each present location where a data error is detected on reading the data from the addressable location comprising, in combination: mode defining means alternatively defining a search mode or a normal mode; address generator means responsive to said mode defining means being in said search mode to generate in succession each possible memory address and to apply the produced address to the memory, the memory producing an indication whether the addressed location is present or not present; storage means responsive to said mode defining means being in said search mode to store for each possible memory address, said indication from the memory indicating whether the addressed location is present or not; said mode defining means being responsive to said address generator means having once produced each possible memory address for which said storage means has stored an indication whether the location is present or not to change the mode to said normal mode; said address generator being responsive to said mode defining means being in said normal mode to periodically generate all possible memory addresses at a rate slower than the rate of address generation during said search mode, said address generator being operative to apply said memory address to said memory if said indication in said storage means for said generated address indicates the corresponding memory location is present.