Memory failure detection apparatus

Claim 1

Apparatus for identifying a defective portion of a memory comprising a plurality of separately replaceable memory boards organized so that first and second memory boards function with a first error correction circuit, wherein third and fourth memory boards function with a second error correction circuit, wherein both said error correction circuits correct and provide an indication of correctable memory errors from their associated memory boards, and wherein board selection apparatus generates signals to select a board of said memory during addressing, said apparatus comprising: first logic means receiving a first signal from said first error correction circuit indicating a correctable memory error from reading said first and said second memory boards, said first logic means also receiving a second signal from said board selection apparatus indicating that said first or said second memory boards have been selected and upon the concurrence of said first signal and said second signal said first logic means provides separate indications of which of said first of said second memory boards has failed; second logic means receiving a third signal from said second error correction circuit indicating a correctable memory error from reading said third and said fourth memory error from reading said third and said fourth memory boards, said second logic means also receiving a fourth signal from said board selection apparatus indicating that said third or said fourth memory boards have been selected and upon the concurrence of said third signal and said fourth signal said second logic means provides separate indications of which of said third or said fourth memory boards has failed; a first counter connected to the output of said first logic means and counting the number of times that said first logic means determines that there is a failure of said first memory board, a second counter connected to the output of said first logic means and counting the number of times that said first logic means determines that there is a failure of said second memory board, a third counter connected to the output of said second logic means and counting the number of times that said second logic means determines that there is a failure of said third memory board, and a fourth counter connected to the output of said second logic means and counting the number of times that said second logic means determines that there is a failure of said fourth memory board, said first, second, third and fourth counters being external to all of said memory boards.