Patent US4916524A successfully refreshed from Google Patents.
US4916524A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Dram cell and method
Assignee: Texas Instruments Inc
•
Filing: 1989-01-23
•
Granted: 1990-04-10
•
Expires: 2009-01-23
Abstract
Abstract The described embodiments of the present invention provide structures, and a method for fabricating those structures, which include a memory cell formed within a single trench. A trench is formed in the surface of a semiconductor substrate. The bottom portion of the trench is filled with polycrystalline silicon to form one plate of a storage capacitor. The substrate serves as the other plate of the capacitor. The remaining portion of the trench is then filled with an insulating material such as silicon dioxide. A pattern is then etched into the silicon dioxide when opens a portion of the sidewall and the top portion of the trench down to the polycrystalline capacitor plate. A contact is then formed between the polycrystalline capacitor plate and the substrate. Dopant atoms diffuse through the contact to form a source region on a sidewall of the trench. A gate insulator is formed by oxidation and a drain is formed at the surface of the trench adjacent to the mouth of the trench. Conductive material is then formed inside the open portion of the upper portion of the trench thereby forming a transistor connecting the upper plate of the storage capacitor to a drain region on the surface of the semiconductor substrate.
Inventors
- 👤 Clarence W. Teng
- 👤 Robert R. Doering
- 👤 Ashwin H. Shah
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 14:49
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/03; H10B12/038; H10B12/0383; H10B12/30; H10B12/39; H10B12/395; H10P; H10P32/00; H10P32/10; H10P32/14; H10P32/1408; H10P32/17; H10P32/171
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
114 words
A memory cell comprising a trench formed in a semiconductor substrate; an insulating layer formed on the walls of said trench; a conductive connection formed through said insulating layer to said substrate providing a conductive path to a source region formed in said substrate on one side of said trench: a drain region formed at the mouth of said trench on said one side of said trench defining a channel region between said source and said drain; an insulating plug filling the remaining portion of said trench excepting a portion of said trench adjacent to said drain region and said source region; and a conductive gate formed in the remaining portion of said trench.
Claim 2
Dependent Claim
114 words
A memory cell comprising a trench formed in a semiconductor substrate; an insulating layer formed on the walls of said trench; a conductive connection formed through said insulating layer to said substrate providing a conductive path to a source region formed in said substrate on one side of said trench: a drain region formed at the mouth of said trench on said one side of said trench defining a channel region between said source and said drain; an insulating plug filling the remaining portion of said trench excepting a portion of said trench adjacent to said drain region and said source region; and a conductive gate formed in the remaining portion of said trench.
Claim 3
Dependent Claim
29 words
The memory cell of claim 1 wherein said trench is in the form of a right rectangular parallelepiped having its major axis perpandicular to a surface of said substrate.
Claim 4
Dependent Claim
18 words
The memory cell of claim 1 wherein said trench has a depth into said substrate of 8 μ.
Claim 5
Dependent Claim
12 words
The memory cell of claim 1 wherein said substrate comprises crystalline silicon.
Claim 6
Dependent Claim
35 words
The memory cell of claim 1 wherein the portion of said insulating layer between said gate and said substrate is thicker than the portion of said insulating layer between said conductive layer and said substrate.
Claim 7
Dependent Claim
35 words
The memory cell of claim 5 wherein said portion of said insulating layer between said gate and said substrate is 250 Å thick and the other portions of said insulating layer are 150 Å thick.
Claim 8
Dependent Claim
131 words
A memory array comprising a plurality of memory cells, each cell comprising a trench formed in a semiconductor substrate; an insulating layer formed on the walls of said trench; a conductive layer filling a portion of said trench; a conductive connection formed through said insulating layer to said substrate providing a conductive path to a source region formed in said substrate on one side of said trench; a drain region formed at the mouth of said trench on said one side of said trench defining a channel region between said source and said drain; an insulating plug filling the remaining portion of said trench excepting a portion of said trench adjacent to said drain region and said source region; and a conductive gate formed in the remaining portion of said trench.
Claim 9
Dependent Claim
131 words
A memory array comprising a plurality of memory cells, each cell comprising a trench formed in a semiconductor substrate; an insulating layer formed on the walls of said trench; a conductive layer filling a portion of said trench; a conductive connection formed through said insulating layer to said substrate providing a conductive path to a source region formed in said substrate on one side of said trench; a drain region formed at the mouth of said trench on said one side of said trench defining a channel region between said source and said drain; an insulating plug filling the remaining portion of said trench excepting a portion of said trench adjacent to said drain region and said source region; and a conductive gate formed in the remaining portion of said trench.
Claim 10
Dependent Claim
29 words
The memory cell of claim 7 wherein said trench is in the form of a right rectangular parallelpiped having its major axis perpandiculur to a surface of said substrate.
Claim 11
Dependent Claim
18 words
The memory cell of claim 7 wherein said trench has a depth into said substrate of 8 μ.
Claim 12
Dependent Claim
12 words
The memory array of claim 7 wherein said substrate comprises crystalline silicon.
Claim 13
Dependent Claim
35 words
The memory array of claim 7 wherein the portion of said insulating layer between said gate and said substrate is thicker than the portion of said insulating layer between said conductive layer and said substrate.
Claim 14
Dependent Claim
35 words
The memory array of claim 7 wherein said portion of said insulating layer between said gate and said substrate is 250 Å thick and the other portions of said insulating layer are 150 Å thick.
References Cited (Backward Citations)
US4240092A
Cited
US4462040A
Cited
JPS58213464A
Cited
JPS59141262A
Cited
US4672410A
Cited
US4651184A
Cited
JPS6173366A
Cited
US4683486A
Cited
EP0187237A2
Cited
EP0186875A2
Cited
US4673962A
Cited
EP0198590A2
Cited
US4649625A
Cited
US4751558A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-04-09 | 1993-10-09 | 1994-04-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-04-09 | 1997-10-09 | 1998-04-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-04-09 | 2001-10-09 | 2002-04-10 | $7700.00 | Window Closed / Lapsed |